From: Konstantinos Margaritis <konstantinos.margaritis@vectorcamp.gr>
Date: Fri, 28 Apr 2023 16:02:26 +0000 (+0000)
Subject: almost there, positive values work, negative values differ by 1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50ec7431bb89eb3c8cf7e7ae70044e235deebad1;p=openpower-isa.git

almost there, positive values work, negative values differ by 1
---

diff --git a/openpower/isa/butterfly.mdwn b/openpower/isa/butterfly.mdwn
index b6fecae2..277305a8 100644
--- a/openpower/isa/butterfly.mdwn
+++ b/openpower/isa/butterfly.mdwn
@@ -6,19 +6,24 @@
 
 A-Form
 
-* maddsubrs  RT,RA,RB,SH
+* maddsubrs  RT,RA,SH,RB
 
 Pseudo-code:
 
-    n <- XLEN-SH
+    n <- SH
     sum <- (RT) + (RA)
     diff <- (RT) - (RA)
-    prod1[0:(XLEN*2)-1] <- MULS(RB, sum)
-    prod2[0:(XLEN*2)-1] <- MULS(RB, diff)
-    res1 <- prod1[XLEN/2-SH:XLEN-1-SH]
-    res2 <- prod2[XLEN/2-SH:XLEN-1-SH]
-    RT <- (RT) + EXTS(res1)
-    RS <- (RS) + EXTS(res2)
+    prod1 <- MULS(RB, sum)[XLEN:(XLEN*2)-1]
+    prod2 <- MULS(RB, diff)[XLEN:(XLEN*2)-1]
+    res1 <- ROTL64(prod1, XLEN-n)
+    res2 <- ROTL64(prod2, XLEN-n)
+    m <- MASK(n, (XLEN-1))
+    s1 <- res1[0]
+    s2 <- res2[0]
+    smask1 <- ([s1]*XLEN) & ¬m
+    smask2 <- ([s2]*XLEN) & ¬m
+    RT <- res1 & m | smask1
+    RS <- res2 & m | smask2
 
 Special Registers Altered:
 
diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text
index b97946a4..451fb57d 100644
--- a/openpower/isatables/fields.text
+++ b/openpower/isatables/fields.text
@@ -213,12 +213,12 @@
 
 # 1.6.17 A-FORM
     |0     |6     |11      |16     |21      |26    |31 |
-    | PO   |  FRT |   FRA  | FRB   |   FRC  |   XO |Rc |
-    | PO   |  FRT |   FRA  | FRB   |    /// |   XO |Rc |
-    | PO   |  FRT |   FRA  |   /// |   FRC  |   XO |Rc |
-    | PO   |  FRT |    /// | FRB   |    /// |   XO |Rc |
-    | PO   |   RT |   RA   |   RB  |    BC  |   XO |  /|
-    | PO   |  RT  |   RA   |   RB  |   SH   |   XO |Rc |
+    | PO   |  FRT |  FRA  |  FRB   |   FRC  |   XO |Rc |
+    | PO   |  FRT |  FRA  |  FRB   |   ///  |   XO |Rc |
+    | PO   |  FRT |  FRA  |  ///   |   FRC  |   XO |Rc |
+    | PO   |  FRT |  ///  |  FRB   |   ///  |   XO |Rc |
+    | PO   |   RT |  RA   |  RB    |   BC   |   XO |  /|
+    | PO   |   RT |  RA   |  RB    |   SH   |   XO |Rc |
 
 # 1.6.18 M-FORM
     |0     |6    |11    |16    |21    |26    |31|
diff --git a/src/openpower/test/alu/maddsubrs_cases.py b/src/openpower/test/alu/maddsubrs_cases.py
index dbee9c5f..9dd48c97 100644
--- a/src/openpower/test/alu/maddsubrs_cases.py
+++ b/src/openpower/test/alu/maddsubrs_cases.py
@@ -13,19 +13,16 @@ import unittest
 class MADDSUBRSTestCase(TestAccumulatorBase):
 
     def case_0_maddsubrs(self):
-        isa = SVP64Asm(["maddsubrs 1,2,3,0"])
+        isa = SVP64Asm(["maddsubrs 1,2,14,3"])
         lst = list(isa)
 
         initial_regs = [0] * 32
         initial_regs[1] = 0x00000a70
-        initial_regs[2] = 0xffffe6b8
+        initial_regs[2] = 0x0000e6b8
         initial_regs[3] = 0x00002d41
 
         e = ExpectedState(pc=4)
-        e.intregs[1] = 0xfffff581
-        e.intregs[11] = 0x00001942
+        e.intregs[1] = 0x0000aa85
+        e.intregs[2] = 0xffffffffffff643e
         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 
-        self.add_case(Program(lst, bigendian), expected=e)
-
-