From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Jan 2019 14:15:23 +0000 (+0100)
Subject: Fix cells_sim.v for Achronix FPGA
X-Git-Tag: yosys-0.9~342^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50ef4561d49a471162799fd1f2cd42af408c0b73;p=yosys.git

Fix cells_sim.v for Achronix FPGA
---

diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index da23fed7e..a94dce9b1 100755
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -61,7 +61,7 @@ reg [1:0]   s1;
   end
 endfunction
 
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
+always @(dataa_w or datab_w or datac_w or datad_w) begin
    combout_rt = lut_data(lut_function, dataa_w, datab_w,
                          datac_w, datad_w);
 end