From: David Shah <dave@ds0.me>
Date: Fri, 22 Nov 2019 08:24:01 +0000 (+0000)
Subject: sv: Add lexing and parsing of .* (wildcard port conns)
X-Git-Tag: working-ls180~824^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50f86c11b2bb9e561f5a0cf10e053b1aa4918abd;p=yosys.git

sv: Add lexing and parsing of .* (wildcard port conns)

Signed-off-by: David Shah <dave@ds0.me>
---

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index ca23df3e8..39520bd51 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -431,6 +431,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 "+:" { return TOK_POS_INDEXED; }
 "-:" { return TOK_NEG_INDEXED; }
 
+".*" { return TOK_AUTOCONNECT_ALL; }
+
 [-+]?[=*]> {
 	if (!specify_mode) REJECT;
 	frontend_verilog_yylval.string = new std::string(yytext);
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index a30935e0a..cb413e13a 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -138,7 +138,7 @@ struct specify_rise_fall {
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
@@ -1580,6 +1580,9 @@ cell_port:
 		node->children.back()->str = *$3;
 		delete $3;
 		free_attr($1);
+	} |
+	attr TOK_AUTOCONNECT_ALL {
+		astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false);
 	};
 
 always_comb_or_latch: