From: Richard Sandiford <richard.sandiford@arm.com>
Date: Mon, 30 Sep 2019 15:23:30 +0000 (+0000)
Subject: [AArch64] Strengthen aarch64_hard_regno_call_part_clobbered
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51051f474a768d285714d713f1b7535d6a139350;p=gcc.git

[AArch64] Strengthen aarch64_hard_regno_call_part_clobbered

The aarch64_vector_pcs handling in aarch64_hard_regno_call_part_clobbered
checks whether the mode might be bigger than 16 bytes, since on SVE
targets the (non-SVE) vector PCS only guarantees that the low 16 bytes
are preserved.  But for multi-register modes, we should instead test
whether each single-register part might be bigger than 16 bytes.
(The size is always divided evenly between registers.)

The testcase uses XImode as an example where this helps.

2019-09-30  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_hard_regno_call_part_clobbered):
	For multi-registers modes, test how big each register part is.

gcc/testsuite/
	* gcc.target/aarch64/torture/simd-abi-8.c: New test.

From-SVN: r276305
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6e453b9ad9d..830c93ddacb 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-09-30  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* config/aarch64/aarch64.c (aarch64_hard_regno_call_part_clobbered):
+	For multi-registers modes, test how big each register part is.
+
 2019-09-30  Nick Clifton  <nickc@redhat.com>
 
 	PR target/59205
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 81d0f2b3f1f..29c070d9b99 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1890,9 +1890,16 @@ static bool
 aarch64_hard_regno_call_part_clobbered (rtx_insn *insn, unsigned int regno,
 					machine_mode mode)
 {
-  bool simd_p = insn && CALL_P (insn) && aarch64_simd_call_p (insn);
-  return FP_REGNUM_P (regno)
-	 && maybe_gt (GET_MODE_SIZE (mode), simd_p ? 16 : 8);
+  if (FP_REGNUM_P (regno))
+    {
+      bool simd_p = insn && CALL_P (insn) && aarch64_simd_call_p (insn);
+      poly_int64 per_register_size = GET_MODE_SIZE (mode);
+      unsigned int nregs = hard_regno_nregs (regno, mode);
+      if (nregs > 1)
+	per_register_size = exact_div (per_register_size, nregs);
+      return maybe_gt (per_register_size, simd_p ? 16 : 8);
+    }
+  return false;
 }
 
 /* Implement TARGET_RETURN_CALL_WITH_MAX_CLOBBERS.  */
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 868b4aa3438..2ac61fffaad 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-09-30  Richard Sandiford  <richard.sandiford@arm.com>
+
+	* gcc.target/aarch64/torture/simd-abi-8.c: New test.
+
 2019-09-30  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* gcc.dg/Wincompatible-pointer-types-1.c (f1): Expect only one
diff --git a/gcc/testsuite/gcc.target/aarch64/torture/simd-abi-8.c b/gcc/testsuite/gcc.target/aarch64/torture/simd-abi-8.c
new file mode 100644
index 00000000000..6463f6c5066
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/torture/simd-abi-8.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-std=gnu99" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } { "" } } */
+
+#include <arm_neon.h>
+
+void __attribute__ ((aarch64_vector_pcs)) f (void);
+
+void
+g (int64x2x4_t *ptr)
+{
+  register int64x2x4_t copy asm ("v8") = *ptr;
+  int64x2x4_t save;
+  asm volatile ("" : "=w" (save) : "0" (copy));
+  f ();
+  *ptr = save;
+}
+
+/* { dg-final { scan-assembler-times {\tld1\t} 1 } } */
+/* { dg-final { scan-assembler-times {\tst1\t} 1 } } */