From: Sa Liu Date: Mon, 7 Jan 2008 13:48:12 +0000 (+0000) Subject: Genetate inline code for double division. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51173714c90a55ef472ae46e55d364e0570ece6d;p=gcc.git Genetate inline code for double division. From-SVN: r131373 --- diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md index 31d2f14c691..f1bfdaff607 100644 --- a/gcc/config/spu/spu.md +++ b/gcc/config/spu/spu.md @@ -1735,6 +1735,58 @@ DONE; }) +;; Taken from STI's gcc +;; Does not correctly handle INF or NAN. +(define_expand "divdf3" + [(set (match_operand:DF 0 "register_operand" "=r") + (div:DF (match_operand:DF 1 "register_operand" "r") + (match_operand:DF 2 "register_operand" "r")))] + "flag_finite_math_only" + "{ + /* + double + divdf3 (double x, double y) + { + float x0; + float y_f = (float) y; + double x1, x2; + + x0 = spu_extract(spu_re(spu_promote(y_f, 0)), 0); + x1 = (double)(x0 * (2.0f - y_f * x0)); + x2 = x1 * (2.0 - y * x1); + return (x * x2 * (2.0 - y * x2)); + } + */ + + rtx dst = operands[0]; + rtx x = operands[1]; + rtx y = operands[2]; + rtx y_f = gen_reg_rtx(SFmode); + rtx x0_f = gen_reg_rtx(SFmode); + rtx x1_f = gen_reg_rtx(SFmode); + rtx x1 = gen_reg_rtx(DFmode); + rtx x2 = gen_reg_rtx(DFmode); + rtx t1_f = gen_reg_rtx(SFmode); + rtx t1 = gen_reg_rtx(DFmode); + rtx two = gen_reg_rtx(DFmode); + rtx two_f = gen_reg_rtx(SFmode); + + emit_insn (gen_truncdfsf2 (y_f, y)); + emit_insn (gen_frest_sf (x0_f, y_f)); + emit_insn (gen_fi_sf (x0_f, y_f, x0_f)); + emit_insn (gen_movsf (two_f, spu_float_const(\"2.0\",SFmode))); + emit_insn (gen_fnms_sf (t1_f, y_f, x0_f, two_f)); + emit_insn (gen_mulsf3 (x1_f, t1_f, x0_f)); + emit_insn (gen_extendsfdf2 (x1, x1_f)); + emit_insn (gen_extendsfdf2 (two, two_f)); + emit_insn (gen_movdf (t1, two)); + emit_insn (gen_fnms_df (t1, y, x1, t1)); + emit_insn (gen_muldf3 (x2, x1, t1)); + emit_insn (gen_fnms_df (two, y, x2, two)); + emit_insn (gen_muldf3 (dst, x2, two)); + emit_insn (gen_muldf3 (dst, dst, x)); + DONE; +}") ;; sqrt