From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 1 Jun 2020 08:58:45 +0000 (+0200)
Subject: soc/interconnect/axi: generate wishbone.sel for reads.
X-Git-Tag: 24jan2021_ls180~251
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=511832a911cbe3f36e78c97d5c642155fb2a74da;p=litex.git

soc/interconnect/axi: generate wishbone.sel for reads.
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 2c444d60..e95e01e0 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -365,6 +365,7 @@ class AXILite2Wishbone(Module):
             wishbone.stb.eq(1),
             wishbone.cyc.eq(1),
             wishbone.adr.eq(_r_addr[wishbone_adr_shift:]),
+            wishbone.sel.eq(2**len(wishbone.sel) - 1),
             If(wishbone.ack,
                 axi_lite.ar.ready.eq(1),
                 NextValue(_data, wishbone.dat_r),