From: Timothy Hayes Date: Mon, 13 Jan 2020 10:26:18 +0000 (+0000) Subject: cpu: Add HtmCpu DebugFlag X-Git-Tag: v20.1.0.0~119 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=511b53387acb19dac6c037709fb2948af9347799;p=gem5.git cpu: Add HtmCpu DebugFlag JIRA: https://gem5.atlassian.net/browse/GEM5-587 Change-Id: Id4b86b8964bc64bce1d2e4af941217eb114f3cc4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30320 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/src/cpu/SConscript b/src/cpu/SConscript index dea7e92a0..194631a17 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -1,5 +1,17 @@ # -*- mode:python -*- +# Copyright (c) 2020 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2006 The Regents of The University of Michigan # All rights reserved. # @@ -51,6 +63,7 @@ DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions') DebugFlag('ExecAsid', 'Format: Include ASID in trace') DebugFlag('ExecFlags', 'Format: Include instruction flags in trace') DebugFlag('Fetch') +DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)') DebugFlag('IntrControl') DebugFlag('O3PipeView') DebugFlag('PCEvent')