From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Sun, 24 Apr 2016 05:33:36 +0000 (-0700)
Subject: Added GP_ACMP cell
X-Git-Tag: yosys-0.7~243^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=512486dcf37f779e6271e299eb186ab2559eb344;p=yosys.git

Added GP_ACMP cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 706e955b6..e6b5db750 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -13,6 +13,18 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
 	assign OUT = INIT[{IN3, IN2, IN1, IN0}];
 endmodule
 
+module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg VOUT = 0);
+
+	parameter BANDWIDTH = "HIGH";
+	parameter VIN_BUF_EN = 0;
+	parameter VIN_ATTEN = 1;
+	parameter VIN_ISRC_EN = 0;
+	parameter HYSTERESIS = 0;
+	
+	//cannot simulate mixed signal IP
+
+endmodule
+
 module GP_BANDGAP(output reg OK, output reg VOUT);
 	parameter AUTO_PWRDN = 1;
 	parameter CHOPPER_EN = 1;