From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 17 Nov 2018 16:36:57 +0000 (+0100)
Subject: test/test_targets: update
X-Git-Tag: 24jan2021_ls180~1486
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5137c2bf884b2c24e0deafdd120823b1817a24f8;p=litex.git

test/test_targets: update
---

diff --git a/test/test_targets.py b/test/test_targets.py
index 615e5448..f6fc56b6 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -57,6 +57,16 @@ class TestTargets(unittest.TestCase):
 
     # lattice boards
 
+    def test_versa_ecp5(self):
+        from litex.boards.targets.versa_ecp5 import BaseSoC
+        errors = build_test([BaseSoC()])
+        self.assertEqual(errors, 0)
+
+    def test_versa_ulx3s(self):
+        from litex.boards.targets.ulx3s import BaseSoC
+        errors = build_test([BaseSoC()])
+        self.assertEqual(errors, 0)
+
     # build simple design for all platforms
     def test_simple(self):
         platforms = [
@@ -76,8 +86,8 @@ class TestTargets(unittest.TestCase):
             "papilio_pro",
             "tinyfpga_b",
             "tinyfpga_bx",
-            "versa",
-            "versaecp55g"
+            "versa_ecp3",
+            "versa_ecp5"
         ]
         for p in platforms:
             os.system("litex_simple litex.boards.platforms." + p +