From: Guozhi Wei <carrot@google.com>
Date: Thu, 4 Sep 2014 16:06:13 +0000 (+0000)
Subject: re PR target/62040 (internal compiler error: in simplify_const_unary_operation, at... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=514372694337432c7b8a2e989384d9bcb64c79ac;p=gcc.git

re PR target/62040 (internal compiler error: in simplify_const_unary_operation, at simplify-rtx.c:1555)

	PR target/62040
	* config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
	* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Split
	it into two patterns.
	(move_lo_quad_internal_be_<mode>): Likewise.

	* gcc.target/aarch64/pr62040.c: New test.

From-SVN: r214905
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index a2db9c2f8a6..48fcf9c443f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2014-09-04  Guozhi Wei  <carrot@google.com>
+
+	PR target/62040
+	* config/aarch64/iterators.md (VQ_NO2E, VQ_2E): New iterators.
+	* config/aarch64/aarch64-simd.md (move_lo_quad_internal_<mode>): Split
+	it into two patterns.
+	(move_lo_quad_internal_be_<mode>): Likewise.
+
 2014-09-04  Manuel López-Ibáñez  <manu@gcc.gnu.org>
 
 	* doc/options.texi: Document that Var and Init are required if CPP
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index f5fa4aebe4c..c4896364f48 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -953,8 +953,8 @@
 ;; On big-endian this is { zeroes, operand }
 
 (define_insn "move_lo_quad_internal_<mode>"
-  [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
-        (vec_concat:VQ
+  [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ_NO2E
 	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")
 	  (vec_duplicate:<VHALF> (const_int 0))))]
   "TARGET_SIMD && !BYTES_BIG_ENDIAN"
@@ -968,9 +968,25 @@
    (set_attr "length" "4")]
 )
 
+(define_insn "move_lo_quad_internal_<mode>"
+  [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ_2E
+	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")
+	  (const_int 0)))]
+  "TARGET_SIMD && !BYTES_BIG_ENDIAN"
+  "@
+   dup\\t%d0, %1.d[0]
+   fmov\\t%d0, %1
+   dup\\t%d0, %1"
+  [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+   (set_attr "simd" "yes,*,yes")
+   (set_attr "fp" "*,yes,*")
+   (set_attr "length" "4")]
+)
+
 (define_insn "move_lo_quad_internal_be_<mode>"
-  [(set (match_operand:VQ 0 "register_operand" "=w,w,w")
-        (vec_concat:VQ
+  [(set (match_operand:VQ_NO2E 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ_NO2E
 	  (vec_duplicate:<VHALF> (const_int 0))
 	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
   "TARGET_SIMD && BYTES_BIG_ENDIAN"
@@ -984,6 +1000,22 @@
    (set_attr "length" "4")]
 )
 
+(define_insn "move_lo_quad_internal_be_<mode>"
+  [(set (match_operand:VQ_2E 0 "register_operand" "=w,w,w")
+	(vec_concat:VQ_2E
+	  (const_int 0)
+	  (match_operand:<VHALF> 1 "register_operand" "w,r,r")))]
+  "TARGET_SIMD && BYTES_BIG_ENDIAN"
+  "@
+   dup\\t%d0, %1.d[0]
+   fmov\\t%d0, %1
+   dup\\t%d0, %1"
+  [(set_attr "type" "neon_dup<q>,f_mcr,neon_dup<q>")
+   (set_attr "simd" "yes,*,yes")
+   (set_attr "fp" "*,yes,*")
+   (set_attr "length" "4")]
+)
+
 (define_expand "move_lo_quad_<mode>"
   [(match_operand:VQ 0 "register_operand")
    (match_operand:VQ 1 "register_operand")]
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 3203c3da7e2..a00283a04b3 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -66,6 +66,12 @@
 ;; Quad vector modes.
 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V4SF V2DF])
 
+;; VQ without 2 element modes.
+(define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V4SF])
+
+;; Quad vector with only 2 element modes.
+(define_mode_iterator VQ_2E [V2DI V2DF])
+
 ;; All vector modes, except double.
 (define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
 
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 2a7e605a107..fb57d87d4a1 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-09-04  Guozhi Wei  <carrot@google.com>
+
+	PR target/62040
+	* gcc.target/aarch64/pr62040.c: New test.
+
 2014-09-04  Manuel López-Ibáñez  <manu@gcc.gnu.org>
 
 	* gcc.dg/cpp/endif-pedantic2.c: More general options do not
diff --git a/gcc/testsuite/gcc.target/aarch64/pr62040.c b/gcc/testsuite/gcc.target/aarch64/pr62040.c
new file mode 100644
index 00000000000..cfb4979f885
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr62040.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+#include "arm_neon.h"
+
+extern void bar (int32x4_t);
+
+void
+foo ()
+{
+  int32x4x4_t rows;
+  uint64x2x2_t row01;
+
+  row01.val[0] = vreinterpretq_u64_s32 (rows.val[0]);
+  row01.val[1] = vreinterpretq_u64_s32 (rows.val[1]);
+  uint64x1_t row3l = vget_low_u64 (row01.val[0]);
+  row01.val[0] = vcombine_u64 (vget_low_u64 (row01.val[1]), row3l);
+  int32x4_t xxx = vreinterpretq_s32_u64 (row01.val[0]);
+  int32x4_t out = vtrn1q_s32 (xxx, xxx);
+  bar (out);
+}