From: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Sun, 27 Feb 2022 08:51:04 +0000 (+0900)
Subject: RISC-V: Fix RV32Q conflict
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51498ab9abc6;p=binutils-gdb.git

RISC-V: Fix RV32Q conflict

This commit makes RV32 + 'Q' extension (version 2.2 or later) not
conflicting since this combination is no longer prohibited by the
specification.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): Remove conflict
	detection that prohibits RV32Q on 'Q' version 2.2 or later.

gas/ChangeLog:

	* testsuite/gas/riscv/march-fail-rv32iq.d: Removed.
	* testsuite/gas/riscv/march-fail-rv32iq.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq2p0.d: New test
	showing RV32IQ fails on 'Q' extension version 2.0.
	* testsuite/gas/riscv/march-fail-rv32iq2p0.l: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq2.d: Likewise.
	* testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d: New test
	showing RV32IQ fails on ISA specification version 2.2.
	* testsuite/gas/riscv/march-ok-rv32iq2p2.d: New test
	showing RV32IQ succesds on 'Q' extension version 2.2.
	* testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d: New test
	showing RV32IQ succesds on ISA specification 20190608.
---

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b2806185fa8..2953dc34b2f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1887,10 +1887,11 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       no_conflict = false;
     }
   if (riscv_lookup_subset (rps->subset_list, "q", &subset)
+      && (subset->major_version < 2 || (subset->major_version == 2
+					&& subset->minor_version < 2))
       && xlen < 64)
     {
-      rps->error_handler
-        (_("rv%d does not support the `q' extension"), xlen);
+      rps->error_handler (_("rv%d does not support the `q' extension"), xlen);
       no_conflict = false;
     }
   if (riscv_lookup_subset (rps->subset_list, "e", &subset)
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
new file mode 100644
index 00000000000..16451b0f43f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq-isa-2p2.d
@@ -0,0 +1,3 @@
+#as: -misa-spec=2.2 -march=rv32iq
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.d b/gas/testsuite/gas/riscv/march-fail-rv32iq.d
deleted file mode 100644
index c289c695cad..00000000000
--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=rv32iq
-#source: empty.s
-#error_output: march-fail-rv32iq.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq.l b/gas/testsuite/gas/riscv/march-fail-rv32iq.l
deleted file mode 100644
index dc201b3d7bf..00000000000
--- a/gas/testsuite/gas/riscv/march-fail-rv32iq.l
+++ /dev/null
@@ -1,2 +0,0 @@
-.*Assembler messages:
-.*Error: .*rv32 does not support the `q' extension
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
new file mode 100644
index 00000000000..34fce730ce5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iq2
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
new file mode 100644
index 00000000000..916f845a970
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.d
@@ -0,0 +1,3 @@
+#as: -march=rv32iq2p0
+#source: empty.s
+#error_output: march-fail-rv32iq2p0.l
diff --git a/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
new file mode 100644
index 00000000000..dc201b3d7bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-fail-rv32iq2p0.l
@@ -0,0 +1,2 @@
+.*Assembler messages:
+.*Error: .*rv32 does not support the `q' extension
diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
new file mode 100644
index 00000000000..8322957948d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-ok-rv32iq-isa-20190608.d
@@ -0,0 +1,5 @@
+#as: -misa-spec=20190608 -march=rv32iq
+#objdump: -dr
+#source: empty.s
+
+.*:     file format elf32-(little|big)riscv
diff --git a/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
new file mode 100644
index 00000000000..1a922bfaa4d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/march-ok-rv32iq2p2.d
@@ -0,0 +1,5 @@
+#as: -march=rv32iq2p2
+#objdump: -dr
+#source: empty.s
+
+.*:     file format elf32-(little|big)riscv