From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Oct 2018 01:11:09 +0000 (+0100)
Subject: add sign-extension bitwidth macros
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=514fb14ef375af151f575e5e9555792d0a81962a;p=riscv-isa-sim.git

add sign-extension bitwidth macros
---

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 6375a1a..f704f35 100644
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -1,6 +1,9 @@
 #ifndef SV_REG_H
 #define SV_REG_H
 
+#define sext_bwid(x,wid) (((sreg_t)(x) << (64-wid)) >> (64-wid))
+#define zext_bwid(x,wid) (((reg_t)(x) << (64-wid)) >> (64-wid))
+
 class sv_sreg_t;
 
 class sv_regbase_t {
@@ -29,7 +32,7 @@ public:
                        0x1, // 8-default/2: default/2
                        0x2, // 8-default*2: default*2
                        0x3  // 8-8: 8
-    };
+                    };
     return tb[elwidth|(r.elwidth<<2)];
     }
 };