From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 11:28:15 +0000 (+0100)
Subject: add some more tests to countzero
X-Git-Tag: div_pipeline~1207
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=515d476d00384f2efd5082bbee79d0398ef445c3;p=soc.git

add some more tests to countzero
---

diff --git a/src/soc/countzero/test/test_countzero.py b/src/soc/countzero/test/test_countzero.py
index 538db15c..e4ca3519 100644
--- a/src/soc/countzero/test/test_countzero.py
+++ b/src/soc/countzero/test/test_countzero.py
@@ -55,6 +55,29 @@ class ZeroCounterTestCase(FHDLTestCase):
             result = yield dut.result_o
             assert result == 59, "result %d" % result
 
+            yield dut.is_32bit_i.eq(1)
+            yield Delay(1e-6)
+            result = yield dut.result_o
+            assert result == 27, "result %d" % result
+
+            yield dut.rs_i.eq(0b1100000100000000)
+            yield dut.is_32bit_i.eq(0)
+            yield dut.count_right_i.eq(0)
+            yield Delay(1e-6)
+            result = yield dut.result_o
+            assert result == 8, "result %d" % result
+
+            yield dut.count_right_i.eq(1)
+            yield Delay(1e-6)
+            result = yield dut.result_o
+            assert result == 55, "result %d" % result
+
+            yield dut.is_32bit_i.eq(1)
+            yield Delay(1e-6)
+            result = yield dut.result_o
+            assert result == 23, "result %d" % result
+
+
         sim.add_process(process)  # or sim.add_sync_process(process), see below
 
         # run test and write vcd