From: lkcl <lkcl@web>
Date: Sat, 17 Sep 2022 10:00:56 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~393
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5162e22321e5af81ed2d9c607e9438fce42d745b;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index ba18e3806..2c575793b 100644
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -716,7 +716,7 @@ Where:
 * SVP64Single (`RESERVED3/4`) is *planned* for a future RFC
   (but needs reserving as part of this RFC)
 * `RESERVED1/2` is available for new general-purpose **never**-Simple-V
-  (non-Vectoriseable) 32-bit encodings
+  (non-Vectoriseable) 32-bit encodings (again, future RFCs)
 * EXT248-263 is for "new" instructions
   which **must** also simultaneously request the corresponding space
   in SVP64, even if the instruction is non-Vectoriseable.
@@ -725,7 +725,7 @@ Where:
   (Public v3.1 1.6.3 definition). Vectorised-EXT001 or EXT009
   is defined as illegal.
 * Any **future** instruction
-  added to EXT000-063 likewise, is **automatically**
+  added to EXT000-063 likewise, must **automatically** be
   assigned corresponding reservations in the SVP64:EXT000-063
   and SVP64Single:EXT000-063 area, regardless of whether the
   instruction is Vectoriseable or not.
@@ -737,7 +737,7 @@ Bit-allocation Summary:
 * QTY 3of 55-bit spaces also exist for future use (longer by 3 bits
   than opcodes allocated in EXT001)
 * Simple-V EXT2nn is restricted to range EXT248-263
-* non-Simple-V EXT2nn is restricted to range EXT200-247
+* non-Simple-V EXT2nn (if ever allocated by a future RFC) is restricted to range EXT200-247
 * Simple-V EXT0nn takes up 50% of PO9 for this and future Simple-V RFCs
 * The clear separation between Simple-V and non-Simple-V means there is
   no possibility of future RFCs encroaching on the others' space.