From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 5 Sep 2019 17:12:47 +0000 (+0200)
Subject: WIP aditional DFF primitives
X-Git-Tag: working-ls180~956^2~26
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5168b6ffa4047340b3412aa17be7e2d7ac587ee1;p=yosys.git

WIP aditional DFF primitives
---

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index c38805b91..aea11d97e 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -1,9 +1,54 @@
+// TODO add these DFF types
+// Primitive Description
+// DFFSE     D Flip-Flop with Clock Enable and Synchronous Set
+// DFFRE     D Flip-Flop with Clock Enable and Synchronous Reset
+
+// DFFNS     D Flip-Flop with Negative-Edge Clock and Synchronous Set
+// DFFNSE    D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
+// DFFNR     D Flip-Flop with Negative-Edge Clock and Synchronous Reset
+// DFFNRE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
+// DFFNP     D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
+// DFFNPE    D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
+// DFFNC     D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
+// DFFNCE    D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
+
+//TODO all DFF* have INIT
+
+// DFFN      D Flip-Flop with Negative-Edge Clock
 module  \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
+// DFF       D Flip-Flop
 module  \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF  #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
 
+// DFFE      D Flip-Flop with Clock Enable
+module  \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+
+// DFFNE     D Flip-Flop with Negative-Edge Clock and Clock Enable
+module  \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
+module  \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
+
+// DFFR      D Flip-Flop with Synchronous Reset
 module  \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
 module  \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
-module  \$__DFFS_PP1_ (input D, C, R, output Q); DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
+
+// DFFS      D Flip-Flop with Synchronous Set
+module  \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule
+module  \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule
+
+// DFFP      D Flip-Flop with Asynchronous Preset
+module  \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
+// DFFC      D Flip-Flop with Asynchronous Clear
+module  \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
+
+// DFFPE     D Flip-Flop with Clock Enable and Asynchronous Preset
+module  \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
+module  \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
+// DFFCE     D Flip-Flop with Clock Enable and Asynchronous Clear
+module  \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
+module  \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
+
 
 module  \$_MUX_ (input A, B, S, output Y); MUX2  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
 module  \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4  _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 98dfef9bf..c8475b28f 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -62,6 +62,8 @@ module DFFR (output reg Q, input D, CLK, RESET);
 	end
 endmodule // DFFR (positive clock edge; synchronous reset)
 
+// TODO add more DFF sim cells
+
 module VCC(output V);
 	assign V = 1;
 endmodule