From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Tue, 23 Dec 2014 14:31:19 +0000 (-0500)
Subject: mem: Hide WriteInvalidate requests from prefetchers
X-Git-Tag: stable_2015_04_15~41
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=516e6046aefd486768d03ba9c58db80e5ad3fff0;p=gem5.git

mem: Hide WriteInvalidate requests from prefetchers

Without this tweak, a prefetcher will happily prefetch data that will
promptly be invalidated and overwritten by a WriteInvalidate.
---

diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 119397bb5..3ab2d76a6 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -83,7 +83,8 @@ BasePrefetcher::observeAccess(const PacketPtr &pkt) const
 {
     Addr addr = pkt->getAddr();
     bool fetch = pkt->req->isInstFetch();
-    bool read= pkt->isRead();
+    bool read = pkt->isRead();
+    bool inv = pkt->isInvalidate();
     bool is_secure = pkt->isSecure();
 
     if (pkt->req->isUncacheable()) return false;
@@ -91,6 +92,7 @@ BasePrefetcher::observeAccess(const PacketPtr &pkt) const
     if (!fetch && !onData) return false;
     if (!fetch && read && !onRead) return false;
     if (!fetch && !read && !onWrite) return false;
+    if (!fetch && !read && inv) return false;
 
     if (onMiss) {
         return !inCache(addr, is_secure) &&