From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Jul 2015 20:44:01 +0000 (+0200)
Subject: Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
X-Git-Tag: yosys-0.6~218
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=516e8828f2e1175b449e45879d19d20e080e2398;p=yosys.git

Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
---

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b7a196602..d7e1f9afa 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -460,7 +460,6 @@ module SB_RAM40_4K (
 			if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
 			if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
 			if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
-			if (!WMASK_I[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
 		end
 	end