From: Dmitry Selyutin Date: Thu, 21 Sep 2023 17:39:52 +0000 (+0300) Subject: syscalls: support RISC-V architectures X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5172b93982f042f5d7a273cb0e92562305c03ccc;p=openpower-isa.git syscalls: support RISC-V architectures --- diff --git a/src/openpower/syscalls/__init__.py b/src/openpower/syscalls/__init__.py index 5888a8bc..c59b47a8 100644 --- a/src/openpower/syscalls/__init__.py +++ b/src/openpower/syscalls/__init__.py @@ -102,11 +102,19 @@ class Dispatcher: yield from sysnums["ppc"]["common"].items() yield from sysnums["ppc"]["64"].items() + def riscv32(sysnums): + yield from sysnums["generic"]["arch32"].items() + + def riscv64(sysnums): + yield from sysnums["generic"]["arch64"].items() + arch = { "i386": i386, "amd64": amd64, "ppc": ppc, "ppc64": ppc64, + "riscv32": riscv32, + "riscv64": riscv64, } sysnums = table["sysnums"] sysargs = table["sysargs"]