From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 16 Apr 2019 19:41:56 +0000 (-0700)
Subject: read_verilog cells_box.v before techmap
X-Git-Tag: working-ls180~1208^2~340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51896953626ddf7cffdbddfe64e8d85264d968a8;p=yosys.git

read_verilog cells_box.v before techmap
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c10e42532..d5e9b80c8 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_luts"))
 		{
 			Pass::call(design, "opt -full");
-			Pass::call(design, "techmap -map +/techmap.v");
 			Pass::call(design, "read_verilog +/xilinx/cells_box.v");
+			Pass::call(design, "techmap -map +/techmap.v");
 			if (abc == "abc9")
 				Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
 			else