From: Paolo Bonzini Date: Mon, 28 Nov 2016 13:21:02 +0000 (+0000) Subject: combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE that isolates a single bit... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51a07549a93a00d5226635749a5eecf55f451984;p=gcc.git combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE that isolates a single bit... gcc: * combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE that isolates a single bit, even if the condition involves subregs. From-SVN: r242917 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5cf1698ad67..83615edeeb2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2016-11-28 Paolo Bonzini + + * combine.c (simplify_if_then_else): Simplify IF_THEN_ELSE + that isolates a single bit, even if the condition involves + subregs. + 2016-11-28 Tamar Christina * config/aarch64/aarch64-simd-builtins.def diff --git a/gcc/combine.c b/gcc/combine.c index ecf674193f7..45d4048b13d 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -6522,14 +6522,22 @@ simplify_if_then_else (rtx x) simplify_shift_const (NULL_RTX, ASHIFT, mode, gen_lowpart (mode, XEXP (cond, 0)), i); - /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */ + /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only + non-zero bit in A is C1. */ if (true_code == NE && XEXP (cond, 1) == const0_rtx && false_rtx == const0_rtx && CONST_INT_P (true_rtx) - && GET_MODE (XEXP (cond, 0)) == mode + && INTEGRAL_MODE_P (GET_MODE (XEXP (cond, 0))) && (UINTVAL (true_rtx) & GET_MODE_MASK (mode)) - == nonzero_bits (XEXP (cond, 0), mode) + == nonzero_bits (XEXP (cond, 0), GET_MODE (XEXP (cond, 0))) && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0) - return XEXP (cond, 0); + { + rtx val = XEXP (cond, 0); + enum machine_mode val_mode = GET_MODE (val); + if (val_mode == mode) + return val; + else if (GET_MODE_PRECISION (val_mode) < GET_MODE_PRECISION (mode)) + return simplify_gen_unary (ZERO_EXTEND, mode, val, val_mode); + } return x; }