From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 13 Aug 2022 21:21:35 +0000 (+0100)
Subject: disable pack/unpack in sv_analysis.py - going to use bits in
X-Git-Tag: sv_maxu_works-initial~165
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51b1abb2b47655b1685484f13e0daf44b534d510;p=openpower-isa.git

disable pack/unpack in sv_analysis.py - going to use bits in
each mode, now.
---

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 68730cd9..ab8fd8c7 100644
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -142,11 +142,13 @@ def create_key(row):
     else:
         res['imm'] = ''
 
+    res['PU'] = '' # disabled (uses modes, now)
+    return res
+
     # pack/unpack, start with LDST with immediate for now
     if (res['imm'] == '1' and res['unit'] == 'LDST' and
         ((res['in'] == '1' and res['outcnt'] == '1') or # LD-imm
          (res['in'] == '2' and res['outcnt'] == '0'))): # ST-imm
-        #print ("PU", res, row)
         res['PU'] = "1"
     else:
         res['PU'] = ''