From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 18 Sep 2015 09:55:31 +0000 (+0200)
Subject: Added detection of "mux inverter" chains in opt_const
X-Git-Tag: yosys-0.6~160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51e1295d79f373133bd48ace30a76add0d294f02;p=yosys.git

Added detection of "mux inverter" chains in opt_const
---

diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 32a804260..6295b8881 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -249,6 +249,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") &&
 					cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1)
 				invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A"));
+			if ((cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == SigSpec(State::S1) && cell->getPort("\\B") == SigSpec(State::S0))
+				invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\S"));
 			if (ct_combinational.cell_known(cell->type))
 				for (auto &conn : cell->connections()) {
 					RTLIL::SigSpec sig = assign_map(conn.second);