From: Alexander Ivchenko Date: Tue, 14 Oct 2014 08:10:42 +0000 (+0000) Subject: AVX-512. 57/n. Extend blend/cmp/brodcast insn patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51e14b05727883f9416be01a46962082328c8309;p=gcc.git AVX-512. 57/n. Extend blend/cmp/brodcast insn patterns. gcc/ * config/i386/sse.md (define_insn "avx512f_blendm"): Delete. (define_insn "_blendm"): New. (define_insn "_blendm"): Ditto.. (define_mode_attr cmp_imm_predicate): Add V8SF, V4DF, V8SI, V4DI, V4SF, V2DF, V4SI, V2DI, V32HI, V64QI, V16HI, V32QI, V8HI, V16QI modes. (define_insn "avx512f_cmp3"): Remove. (define_insn "_cmp3"): New. (define_insn "_cmp3"): Ditto. (define_insn "avx512f_vec_dup"): Delete. (define_insn "_vec_dup"): New. (define_insn "_vec_dup"): Ditto. (define_insn "avx512f_vec_dup_gpr"): Delete. (define_insn "_vec_dup_gpr"): New. (define_insn "_vec_dup_gpr"): Ditto. (define_insn·"avx512f_vec_dup_mem"): Delete. (define_insn "_vec_dup_mem"): New. (define_insn "_vec_dup_mem"): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r216175 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c7aa8f603f4..0a4673c98a8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,47 @@ +2014-10-14 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_insn "avx512f_blendm"): Delete. + (define_insn "_blendm"): New. + (define_insn "_blendm"): Ditto.. + (define_mode_attr cmp_imm_predicate): Add V8SF, V4DF, V8SI, V4DI, V4SF, + V2DF, V4SI, V2DI, V32HI, V64QI, V16HI, V32QI, V8HI, V16QI modes. + (define_insn + "avx512f_cmp3"): + Remove. + (define_insn + "_cmp3"): + New. + (define_insn + "_cmp3"): + Ditto. + (define_insn "avx512f_vec_dup"): Delete. + (define_insn "_vec_dup"): New. + (define_insn "_vec_dup"): Ditto. + (define_insn "avx512f_vec_dup_gpr"): + Delete. + (define_insn + "_vec_dup_gpr"): + New. + (define_insn + "_vec_dup_gpr"): + Ditto. + (define_insn·"avx512f_vec_dup_mem"): + Delete. + (define_insn + "_vec_dup_mem"): + New. + (define_insn + "_vec_dup_mem"): + Ditto. + 2014-10-14 Richard Biener PR tree-optimization/63512 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e7646d77753..d544ed0676e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -959,14 +959,26 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) -(define_insn "avx512f_blendm" - [(set (match_operand:VI48F_512 0 "register_operand" "=v") - (vec_merge:VI48F_512 - (match_operand:VI48F_512 2 "nonimmediate_operand" "vm") - (match_operand:VI48F_512 1 "register_operand" "v") +(define_insn "_blendm" + [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v") + (vec_merge:V48_AVX512VL + (match_operand:V48_AVX512VL 2 "nonimmediate_operand" "vm") + (match_operand:V48_AVX512VL 1 "register_operand" "v") (match_operand: 3 "register_operand" "Yk")))] "TARGET_AVX512F" - "vblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" + "vblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "_blendm" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_merge:VI12_AVX512VL + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm") + (match_operand:VI12_AVX512VL 1 "register_operand" "v") + (match_operand: 3 "register_operand" "Yk")))] + "TARGET_AVX512BW" + "vpblendm\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}" [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) @@ -2472,14 +2484,21 @@ (set_attr "mode" "")]) (define_mode_attr cmp_imm_predicate - [(V16SF "const_0_to_31_operand") (V8DF "const_0_to_31_operand") - (V16SI "const_0_to_7_operand") (V8DI "const_0_to_7_operand")]) - -(define_insn "avx512f_cmp3" + [(V16SF "const_0_to_31_operand") (V8DF "const_0_to_31_operand") + (V16SI "const_0_to_7_operand") (V8DI "const_0_to_7_operand") + (V8SF "const_0_to_31_operand") (V4DF "const_0_to_31_operand") + (V8SI "const_0_to_7_operand") (V4DI "const_0_to_7_operand") + (V4SF "const_0_to_31_operand") (V2DF "const_0_to_31_operand") + (V4SI "const_0_to_7_operand") (V2DI "const_0_to_7_operand") + (V32HI "const_0_to_7_operand") (V64QI "const_0_to_7_operand") + (V16HI "const_0_to_7_operand") (V32QI "const_0_to_7_operand") + (V8HI "const_0_to_7_operand") (V16QI "const_0_to_7_operand")]) + +(define_insn "_cmp3" [(set (match_operand: 0 "register_operand" "=Yk") (unspec: - [(match_operand:VI48F_512 1 "register_operand" "v") - (match_operand:VI48F_512 2 "" "") + [(match_operand:V48_AVX512VL 1 "register_operand" "v") + (match_operand:V48_AVX512VL 2 "nonimmediate_operand" "") (match_operand:SI 3 "" "n")] UNSPEC_PCMP))] "TARGET_AVX512F && " @@ -2489,6 +2508,20 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "_cmp3" + [(set (match_operand: 0 "register_operand" "=Yk") + (unspec: + [(match_operand:VI12_AVX512VL 1 "register_operand" "v") + (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "" "n")] + UNSPEC_PCMP))] + "TARGET_AVX512BW" + "vpcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "ssecmp") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx512f_ucmp3" [(set (match_operand: 0 "register_operand" "=Yk") (unspec: @@ -16016,13 +16049,13 @@ #" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "isa" "*,avx2,noavx2") (set_attr "mode" "V8SF")]) -(define_insn "avx512f_vec_dup" - [(set (match_operand:VI48F_512 0 "register_operand" "=v") - (vec_duplicate:VI48F_512 +(define_insn "_vec_dup" + [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:V48_AVX512VL (vec_select: (match_operand: 1 "nonimmediate_operand" "vm") (parallel [(const_int 0)]))))] @@ -16032,6 +16065,18 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "_vec_dup" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:VI12_AVX512VL + (vec_select: + (match_operand: 1 "nonimmediate_operand" "vm") + (parallel [(const_int 0)]))))] + "TARGET_AVX512BW" + "vpbroadcast\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx512f_broadcast" [(set (match_operand:V16FI 0 "register_operand" "=v,v") (vec_duplicate:V16FI @@ -16056,19 +16101,31 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vec_dup_gpr" - [(set (match_operand:VI48_512 0 "register_operand" "=v") - (vec_duplicate:VI48_512 +(define_insn "_vec_dup_gpr" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:VI12_AVX512VL (match_operand: 1 "register_operand" "r")))] - "TARGET_AVX512F && (mode != V8DImode || TARGET_64BIT)" - "vpbroadcast\t{%1, %0|%0, %1}" + "TARGET_AVX512BW" + "vpbroadcast\t{%k1, %0|%0, %k1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "_vec_dup_gpr" + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:VI48_AVX512VL + (match_operand: 1 "register_operand" "r")))] + "TARGET_AVX512F && (mode != DImode || TARGET_64BIT)" +{ + return "vpbroadcast\t{%1, %0|%0, %1}"; +} [(set_attr "type" "ssemov") (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_vec_dup_mem" - [(set (match_operand:VI48F_512 0 "register_operand" "=v") - (vec_duplicate:VI48F_512 +(define_insn "_vec_dup_mem" + [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:V48_AVX512VL (match_operand: 1 "nonimmediate_operand" "vm")))] "TARGET_AVX512F" "vbroadcast\t{%1, %0|%0, %1}" @@ -16076,6 +16133,16 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_insn "_vec_dup_mem" + [(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v") + (vec_duplicate:VI12_AVX512VL + (match_operand: 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512BW" + "vpbroadcast\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "avx2_vbroadcasti128_" [(set (match_operand:VI_256 0 "register_operand" "=x") (vec_concat:VI_256