From: William D. Jones <thor0505@comcast.net>
Date: Tue, 15 Jan 2019 20:13:47 +0000 (-0500)
Subject: hdl.ast: Add AnyConst and AnySeq value types.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51e193b6dd33e67b84b9c4010f273ec07d67e9d1;p=nmigen.git

hdl.ast: Add AnyConst and AnySeq value types.
---

diff --git a/nmigen/__init__.py b/nmigen/__init__.py
index 9c3c777..473e8de 100644
--- a/nmigen/__init__.py
+++ b/nmigen/__init__.py
@@ -1,4 +1,4 @@
-from .hdl.ast import Value, Const, C, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume
+from .hdl.ast import Value, Const, C, AnyConst, AnySeq, Mux, Cat, Repl, Array, Signal, ClockSignal, ResetSignal, Assert, Assume
 from .hdl.dsl import Module
 from .hdl.cd import ClockDomain
 from .hdl.ir import Fragment, Instance
diff --git a/nmigen/hdl/ast.py b/nmigen/hdl/ast.py
index 6e95611..5a03ef7 100644
--- a/nmigen/hdl/ast.py
+++ b/nmigen/hdl/ast.py
@@ -9,7 +9,7 @@ from ..tools import *
 
 
 __all__ = [
-    "Value", "Const", "C", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
+    "Value", "Const", "C", "AnyConst", "AnySeq", "Operator", "Mux", "Part", "Slice", "Cat", "Repl",
     "Array", "ArrayProxy",
     "Signal", "ClockSignal", "ResetSignal",
     "Statement", "Assign", "Assert", "Assume", "Switch", "Delay", "Tick",
@@ -254,6 +254,32 @@ class Const(Value):
 C = Const  # shorthand
 
 
+class AnyValue(Value):
+    def __init__(self, shape):
+        super().__init__(src_loc_at=0)
+        if isinstance(shape, int):
+            shape = shape, False
+        self.nbits, self.signed = shape
+        if not isinstance(self.nbits, int) or self.nbits < 0:
+            raise TypeError("Width must be a non-negative integer, not '{!r}'", self.nbits)
+
+    def shape(self):
+        return self.nbits, self.signed
+
+    def _rhs_signals(self):
+        return ValueSet()
+
+
+class AnyConst(AnyValue):
+    def __repr__(self):
+        return "(anyconst {}'{})".format(self.nbits, "s" if self.signed else "")
+
+
+class AnySeq(AnyValue):
+    def __repr__(self):
+        return "(anyseq {}'{})".format(self.nbits, "s" if self.signed else "")
+
+
 class Operator(Value):
     def __init__(self, op, operands, src_loc_at=0):
         super().__init__(src_loc_at=1 + src_loc_at)