From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 May 2019 14:41:44 +0000 (+0100)
Subject: tidy imports
X-Git-Tag: ls180-24jan2020~1070
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51e654f4aa5b4a6c1df58776715fc017966f18b9;p=ieee754fpu.git

tidy imports
---

diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py
index 204a7d18..cfc401e8 100644
--- a/src/ieee754/add/test_fsm_experiment.py
+++ b/src/ieee754/add/test_fsm_experiment.py
@@ -6,8 +6,8 @@ from nmigen import Module, Signal, Const, Cat, Elaboratable
 from nmigen.cli import main, verilog, rtlil
 from nmigen.compat.sim import run_simulation
 
-
-from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState
+from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
+                                     FPOpOut, FPBase)
 from nmutil.nmoperator import eq
 from nmutil.singlepipe import SimpleHandshake, ControlBase
 from test_buf_pipe import data_chain2, Test5