From: lkcl <lkcl@web>
Date: Sat, 16 Jan 2021 17:43:38 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~439
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51f2ad75de59c664443450f6bcd90c8ae7c278a6;p=libreriscv.git

---

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 4b36e1bf9..46d9fe8b8 100644
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -528,7 +528,7 @@ Fields are as follows:
 alternative which is understandable and, if EXTRA2 is zero will map to
 "no effect" i.e Scalar OpenPOWER register naming:
 
-| R\*\_EXTRA2 | Mode | Range/inc | 6..0 |
+| Value | Mode | Range/inc | 6..0 |
 |-----------|-------|---------------|-----------|
 | 00       | Scalar | `r0-r31`/1 | `0b00 RA`     |
 | 01       | Scalar | `r32-r63`/1 | `0b01 RA`      |