From: Florent Kermarrec Date: Tue, 7 Jul 2020 10:11:47 +0000 (+0200) Subject: build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput. X-Git-Tag: 24jan2021_ls180~99 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51f2e6ce6440cd870a7ce8d68b550c52d5e5e313;p=litex.git build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput. --- diff --git a/litex/build/io.py b/litex/build/io.py index f18f08ac..42f9531e 100644 --- a/litex/build/io.py +++ b/litex/build/io.py @@ -81,8 +81,8 @@ class InferedSDRTristate(Module): _o = Signal() _oe = Signal() _i = Signal() - self.specials += SDROutput(o, _o) - self.specials += SDRInput(_i, i) + self.specials += SDROutput(o, _o, clk) + self.specials += SDRInput(_i, i, clk) self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain) self.specials += Tristate(io, _o, _oe, _i)