From: Benjamin Herrenschmidt Date: Tue, 12 May 2020 11:35:12 +0000 (+1000) Subject: soc_core: Add option to override CSR base X-Git-Tag: 24jan2021_ls180~353^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=520c17e96d6fcba23de9435bc6f38379da09d7ec;p=litex.git soc_core: Add option to override CSR base When creating standalone IP cores such as standalone LiteDRAM without a CPU, the CSR are presented externally via a wishbone with just enough address bits to access individual CSRs (14), and no address decoding otherwise. It is expected that the design using such core will have its own address decoder gating cyc/stb. However, such a design might still need to use LiteX code such as the sdram init code, which relies on the generated csr.h. Thus we want to be able to control the CSR base address used by that generated csr.h. This could be handled instead by having the "host" code provide modified csr_{read,write}_simple() that include the necessary base address. However, such an approach would make things complicated if the design includes multiple such standalone cores with separate CSR busses (such as LiteDRAM and LiteEth). Signed-off-by: Benjamin Herrenschmidt --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 68499ad2..6873659c 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -85,6 +85,7 @@ class SoCCore(LiteXSoC): csr_alignment = 32, csr_address_width = 14, csr_paging = 0x800, + csr_base = None, # Identifier parameters ident = "", ident_version = False, @@ -183,7 +184,9 @@ class SoCCore(LiteXSoC): if with_timer: self.add_timer(name="timer0") - # Add CSR bridge + # Add CSR bridge. Potentially override CSR base + if csr_base is not None: + self.mem_map["csr"] = csr_base; self.add_csr_bridge(self.mem_map["csr"]) # Methods --------------------------------------------------------------------------------------