From: Jakub Jelinek Date: Tue, 24 May 2016 19:10:55 +0000 (+0200) Subject: sse.md (sse4_1_v8qiv8hi2): Limit first two alternatives to noavx... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=520c86db4c15e5dbecd68cf79629703fc1bb14b9;p=gcc.git sse.md (sse4_1_v8qiv8hi2): Limit first two alternatives to noavx... * config/i386/sse.md (sse4_1_v8qiv8hi2): Limit first two alternatives to noavx, use *x instead of *v in the second one, add avx alternative without *. (sse4_1_v4qiv4si2, sse4_1_v4hiv4si2, sse4_1_v2qiv2di2, sse4_1_v2hiv2di2, sse4_1_v2siv2di2): Likewise. From-SVN: r236659 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9442109e448..f6bc9451c48 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-05-24 Jakub Jelinek + + * config/i386/sse.md (sse4_1_v8qiv8hi2): Limit + first two alternatives to noavx, use *x instead of *v in the second + one, add avx alternative without *. + (sse4_1_v4qiv4si2, sse4_1_v4hiv4si2, + sse4_1_v2qiv2di2, sse4_1_v2hiv2di2, + sse4_1_v2siv2di2): Likewise. + 2016-05-24 Jeff Law * tree-ssa-threadbackwards.c (convert_and_register_jump_thread_path): diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 745b6b665f5..742c83ea13c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14748,19 +14748,20 @@ (set_attr "mode" "XI")]) (define_insn "sse4_1_v8qiv8hi2" - [(set (match_operand:V8HI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] "TARGET_SSE4_1 && && " "%vpmovbw\t{%1, %0|%0, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_v16qiv16si2" @@ -14790,17 +14791,18 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_v4qiv4si2" - [(set (match_operand:V4SI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI (vec_select:V4QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1 && " "%vpmovbd\t{%1, %0|%0, %k1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_v16hiv16si2" @@ -14825,17 +14827,18 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_v4hiv4si2" - [(set (match_operand:V4SI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1 && " "%vpmovwd\t{%1, %0|%0, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_v8qiv8di2" @@ -14868,16 +14871,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_v2qiv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && " "%vpmovbq\t{%1, %0|%0, %w1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_v8hiv8di2" @@ -14905,16 +14909,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_v2hiv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2HI - (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && " "%vpmovwq\t{%1, %0|%0, %k1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_v8siv8di2" @@ -14939,16 +14944,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_v2siv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V4SI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && " "%vpmovdq\t{%1, %0|%0, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) ;; ptestps/ptestpd are very similar to comiss and ucomiss when