From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 20 Jun 2020 12:16:00 +0000 (+0100)
Subject: add asserts to check data output is correct
X-Git-Tag: div_pipeline~302
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52215e08906096690085424fb4302c694f0793df;p=soc.git

add asserts to check data output is correct
---

diff --git a/src/soc/bus/test/test_sram_wishbone.py b/src/soc/bus/test/test_sram_wishbone.py
index 0a25314a..dfebb3b8 100644
--- a/src/soc/bus/test/test_sram_wishbone.py
+++ b/src/soc/bus/test/test_sram_wishbone.py
@@ -54,10 +54,15 @@ def process():
 
     # see sync_behaviors.py
     # for why we need Settle()
+    # debug print the bus address/data
     yield Settle()
     yield from print_sig(sram.bus.adr)
     yield from print_sig(sram.bus.dat_r, "h")
 
+    # check the result
+    data = yield sram.bus.dat_r
+    assert data == 0
+
     # set necessary signal to read bus
     # at address 4
     yield sram.bus.we.eq(0)
@@ -66,10 +71,17 @@ def process():
     yield sram.bus.stb.eq(1)
     yield
 
+    # see sync_behaviors.py
+    # for why we need Settle()
+    # debug print the bus address/data
     yield Settle()
     yield from print_sig(sram.bus.adr)
     yield from print_sig(sram.bus.dat_r, "h")
 
+    # check the result
+    data = yield sram.bus.dat_r
+    assert data == 0xdeadbeef
+
     # disable signals
     yield sram.bus.cyc.eq(0)
     yield sram.bus.stb.eq(0)