From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sun, 31 May 2015 22:47:11 +0000 (-0700)
Subject: Fix performance bug when CSR accesses are common
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5235a77475ff00aecafb9db4c1b003043d2d7f20;p=riscv-isa-sim.git

Fix performance bug when CSR accesses are common

processor_t::step was returning without doing much work, causing the HTIF
to be ticked far more often than necessary.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index b8e848b..7162a39 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -280,6 +280,10 @@ void processor_t::step(size_t n)
   }
 
   update_timer(&state, instret);
+
+  // tail-recurse if we didn't execute as many instructions as we'd hoped
+  if (instret < n)
+    step(n - instret);
 }
 
 void processor_t::push_privilege_stack()