From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 30 May 2020 19:39:08 +0000 (+0100)
Subject: add in use of "Settle"
X-Git-Tag: div_pipeline~730
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=524264b082757722605cf96540690543cc322004;p=soc.git

add in use of "Settle"
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 3e2c453c..434ab393 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -15,7 +15,7 @@ Links:
 
 """
 
-from nmigen.compat.sim import run_simulation
+from nmigen.compat.sim import run_simulation, Settle
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Elaboratable, Array, Cat
 from nmutil.iocontrol import RecordObject
@@ -532,16 +532,19 @@ def l0_cache_ldst(dut):
 def data_merger_merge(dut):
     print("data_merger")
     #starting with all inputs zero
+    yield Settle()
     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert en == 0, "en must be zero"
     assert data == 0, "data must be zero"
     yield
+
     yield dut.addr_array_i[0].eq(0xFF)
     for j in range(dut.array_size):
         yield dut.data_i[j].en.eq(1 << j)
         yield dut.data_i[j].data.eq(0xFF << (16*j))
-    yield
+    yield Settle()
+
     en = yield dut.data_o.en
     data = yield dut.data_o.data
     assert data == 0xff00ff00ff00ff00ff00ff00ff00ff