From: lkcl <lkcl@web>
Date: Thu, 10 Dec 2020 16:16:28 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1435
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52519ef13253e9a02edde6649a434a81d3358d0e;p=libreriscv.git

---

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 296cd5254..f3880584a 100644
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -56,6 +56,15 @@ One of the issues with vector ops is that in integer DSP ops for example in Audi
 
 If there are spare bits it would be very good to look at using some of them to specify the mode, because otherwise a SPR has to be used which will need to be set and unset.  This can get costly.
 
+Idea: 2 bits for clamping mode? similar to elwidth:
+
+* 0b00 default (no clamp)
+* 0b01 8 bit (sel: -128/127, us:0/255)
+* 0b10 16 bit
+* 0b11 32 bit
+
+not the same *as* elwidth.
+
 # Notes about Swizzle
 
 Basically, there isn't enough room to try to fit two src src1/2 swizzle, and SV, even into 64 bit (actually 24) without severely compromising on the number of bits allocated to either swizzle, or SV, or both.