From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 31 May 2018 16:05:47 +0000 (+0100)
Subject: add RGB565 example
X-Git-Tag: convert-csv-opcode-to-binary~5326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=525523d0a0a1aa84eebac97c474563e3f1dae459;p=libreriscv.git

add RGB565 example
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 498ed9fae..79f4a699a 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -277,15 +277,16 @@ for (int i = 0; i < VL; ++i)
 \frame{\frametitle{Why are overlaps allowed in Regfiles?}
 
  \begin{itemize}
-   \item Same register(s) can have multiple "interpretations"\vspace{10pt}
-   \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{10pt}
-   \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{10pt}
-   \item Same register(s) can be offset (no need for VSLIDE)\vspace{10pt}
+   \item Same register(s) can have multiple "interpretations"\vspace{6pt}
+   \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{6pt}
+   \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{6pt}
+   \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\vspace{6pt}
+   \item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
   \end{itemize}
   Note:\vspace{10pt}
    \begin{itemize}
-   \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$) \vspace{10pt}
-   \item Hi-Performance: Macro-op fusion (more pipeline stages?)\vspace{10pt}
+   \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$)
+   \item Hi-Performance: Macro-op fusion (more pipeline stages?)
   \end{itemize}
 }