From: Hongtao Liu Date: Wed, 5 Jun 2019 06:04:22 +0000 (+0000) Subject: re PR target/89803 (Missing AVX512 intrinsics) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5259a047c31c5a8c13eba73c914ca325e85eb699;p=gcc.git re PR target/89803 (Missing AVX512 intrinsics) gcc/ 2019-06-05 Hongtao Liu PR target/89803 * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask, _mm_mask_fpclass_sd_mask): New intrinsics. (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins. * config/i386/i386-builtin.def (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): New builtins. (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted. * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT), DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted. * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT, case QI_FTYPE_V2SF_INT): Ditto. * config/i386/sse.md (define_insn "avx512dq_vmfpclass): Extended to insnstructions with mask operands. gcc/testsuite 2019-06-05 Hongtao Liu PR target/89803 * gcc.target/i386/avx-1.c (__builtin_ia32_fpclasssss, __builtin_ia32_fpclasssd): Removed. (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. * gcc.target/i386/sse-13.c (__builtin_ia32_fpclasssss, __builtin_ia32_fpclasssd): Removed. (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. * gcc.target/i386/sse-23.c (__builtin_ia32_fpclasssss, __builtin_ia32_fpclasssd): Removed. (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. * gcc.target/i386/avx512dq-vfpclassss-2.c: New. * gcc.target/i386/avx512dq-vfpclasssd-2.c: New. * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): Add test for _mm_mask_fpclass_ss_mask. * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): Add test for _mm_mask_fpclass_sd_mask. From-SVN: r271946 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 526ed45be89..401ba9c58f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,21 @@ +2019-06-05 Hongtao Liu + + PR target/89803 + * config/i386/avx512dqintrin.h (_mm_mask_fpclass_ss_mask, + _mm_mask_fpclass_sd_mask): New intrinsics. + (_mm_fpclass_ss_mask, _mm_fpclass_sd_mask): Modified, use new builtins. + * config/i386/i386-builtin.def + (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): + New builtins. + (__builtin_ia32_fpclassss, __builtin_ia32_fpclasssd): Deleted. + * config/i386/i386-builtin-types.def (DEF_FUNCTION_TYPE (QI, V2DF, INT), + DEF_FUNCTION_TYPE (QI, V4SF, INT)): Deleted. + * config/i386/i386-expand.c (case QI_FTYPE_V4SF_INT, + case QI_FTYPE_V2SF_INT): Ditto. + * config/i386/sse.md + (define_insn "avx512dq_vmfpclass): + Extended to insnstructions with mask operands. + 2019-06-04 Segher Boessenkool * config/rs6000/constraints.md (define_register_constraint "wp"): diff --git a/gcc/config/i386/avx512dqintrin.h b/gcc/config/i386/avx512dqintrin.h index f0c18fb45fb..71c86fcc1c2 100644 --- a/gcc/config/i386/avx512dqintrin.h +++ b/gcc/config/i386/avx512dqintrin.h @@ -1362,14 +1362,30 @@ extern __inline __mmask8 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_fpclass_ss_mask (__m128 __A, const int __imm) { - return (__mmask8) __builtin_ia32_fpclassss ((__v4sf) __A, __imm); + return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, + (__mmask8) -1); } extern __inline __mmask8 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) _mm_fpclass_sd_mask (__m128d __A, const int __imm) { - return (__mmask8) __builtin_ia32_fpclasssd ((__v2df) __A, __imm); + return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, + (__mmask8) -1); +} + +extern __inline __mmask8 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fpclass_ss_mask (__mmask8 __U, __m128 __A, const int __imm) +{ + return (__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) __A, __imm, __U); +} + +extern __inline __mmask8 +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_fpclass_sd_mask (__mmask8 __U, __m128d __A, const int __imm) +{ + return (__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) __A, __imm, __U); } extern __inline __m512i @@ -2617,11 +2633,21 @@ _mm512_fpclass_ps_mask (__m512 __A, const int __imm) (__v16si)(__m512i)_mm512_setzero_si512 (),\ (__mmask16)(U))) -#define _mm_fpclass_ss_mask(X, C) \ - ((__mmask8) __builtin_ia32_fpclassss ((__v4sf) (__m128) (X), (int) (C))) \ +#define _mm_fpclass_ss_mask(X, C) \ + ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), \ + (int) (C), (__mmask8) (-1))) \ + +#define _mm_fpclass_sd_mask(X, C) \ + ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), \ + (int) (C), (__mmask8) (-1))) \ + +#define _mm_mask_fpclass_ss_mask(X, C, U) \ + ((__mmask8) __builtin_ia32_fpclassss_mask ((__v4sf) (__m128) (X), \ + (int) (C), (__mmask8) (U))) -#define _mm_fpclass_sd_mask(X, C) \ - ((__mmask8) __builtin_ia32_fpclasssd ((__v2df) (__m128d) (X), (int) (C))) \ +#define _mm_mask_fpclass_sd_mask(X, C, U) \ + ((__mmask8) __builtin_ia32_fpclasssd_mask ((__v2df) (__m128d) (X), \ + (int) (C), (__mmask8) (U))) #define _mm512_mask_fpclass_pd_mask(u, X, C) \ ((__mmask8) __builtin_ia32_fpclasspd512_mask ((__v8df) (__m512d) (X), \ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 72469e36ae2..4d190604904 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -964,11 +964,9 @@ DEF_FUNCTION_TYPE (V4DI, V4DI, V2DI, V4DI, UQI) DEF_FUNCTION_TYPE (QI, V8DF, INT) DEF_FUNCTION_TYPE (QI, V4DF, INT) DEF_FUNCTION_TYPE (QI, V4DF, V4DF, INT, UQI) -DEF_FUNCTION_TYPE (QI, V2DF, INT) DEF_FUNCTION_TYPE (HI, V16SF, INT) DEF_FUNCTION_TYPE (QI, V8SF, INT) DEF_FUNCTION_TYPE (QI, V8SF, V8SF, INT, UQI) -DEF_FUNCTION_TYPE (QI, V4SF, INT) DEF_FUNCTION_TYPE (QI, V8DF, INT, UQI) DEF_FUNCTION_TYPE (QI, V4DF, INT, UQI) DEF_FUNCTION_TYPE (QI, V2DF, INT, UQI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index b734f63a1c6..e547dda80f1 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2085,10 +2085,10 @@ BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_i BDESC (OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv2df_mask, "__builtin_ia32_fpclasssd_mask", IX86_BUILTIN_FPCLASSSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI) -BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT) +BDESC (OPTION_MASK_ISA_AVX512DQ, 0, CODE_FOR_avx512dq_vmfpclassv4sf_mask, "__builtin_ia32_fpclassss_mask", IX86_BUILTIN_FPCLASSSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI) BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI) diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 01ac5ea3f54..97914536ce4 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -9272,8 +9272,6 @@ ix86_expand_args_builtin (const struct builtin_description *d, case V4DI_FTYPE_V4DI_INT: case V2DI_FTYPE_V4DI_INT: case V4DI_FTYPE_V8DI_INT: - case QI_FTYPE_V4SF_INT: - case QI_FTYPE_V2DF_INT: case UQI_FTYPE_UQI_UQI_CONST: case UHI_FTYPE_UHI_UQI: case USI_FTYPE_USI_UQI: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f8e6f4c5be0..d21f4fc0f60 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21327,7 +21327,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512dq_vmfpclass" +(define_insn "avx512dq_vmfpclass" [(set (match_operand: 0 "register_operand" "=k") (and: (unspec: @@ -21336,7 +21336,7 @@ UNSPEC_FPCLASS) (const_int 1)))] "TARGET_AVX512DQ" - "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; [(set_attr "type" "sse") (set_attr "length_immediate" "1") (set_attr "prefix" "evex") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index ac3e176a8f2..0de9ad902ce 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,22 @@ +2019-06-05 Hongtao Liu + + PR target/89803 + * gcc.target/i386/avx-1.c (__builtin_ia32_fpclasssss, + __builtin_ia32_fpclasssd): Removed. + (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. + * gcc.target/i386/sse-13.c (__builtin_ia32_fpclasssss, + __builtin_ia32_fpclasssd): Removed. + (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. + * gcc.target/i386/sse-23.c (__builtin_ia32_fpclasssss, + __builtin_ia32_fpclasssd): Removed. + (__builtin_ia32_fpclassss_mask, __builtin_ia32_fpclasssd_mask): Define. + * gcc.target/i386/avx512dq-vfpclassss-2.c: New. + * gcc.target/i386/avx512dq-vfpclasssd-2.c: New. + * gcc.target/i386/avx512dq-vfpclassss-1.c (avx512f_test): + Add test for _mm_mask_fpclass_ss_mask. + * gcc.target/i386/avx512dq-vfpclasssd-1.c (avx512f_test): + Add test for _mm_mask_fpclass_sd_mask. + 2019-06-04 Segher Boessenkool * gcc.target/powerpc/direct-move-double1.c (VSX_REG_ATTR): Delete. diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index e09f5a17984..741b3c4f8e3 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -444,8 +444,8 @@ #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E) #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) -#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) -#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U) #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D) diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c index 2d654177ee9..fb5c1d57035 100644 --- a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512dq -O2" } */ /* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclasssd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -11,4 +12,5 @@ void extern avx512dq_test (void) { m8 = _mm_fpclass_sd_mask (x128, 13); + m8 = _mm_mask_fpclass_sd_mask (m8, x128, 13); } diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c new file mode 100644 index 00000000000..469ddc3b86b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclasssd-2.c @@ -0,0 +1,75 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-require-effective-target avx512dq } */ + +#define AVX512DQ +#include "avx512f-helper.h" + +#include +#include +#include +#define SIZE (128 / 64) +#include "avx512f-mask-type.h" + +#ifndef __FPCLASSSD__ +#define __FPCLASSSD__ +int check_fp_class_dp (double src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +__mmask8 +CALC (double *s1, int imm) +{ + int i; + __mmask8 res = 0; + + if (check_fp_class_dp(s1[0], imm)) + res = res | 1; + + return res; +} + +void +TEST (void) +{ + int i; + union128d src; + __mmask8 res1, res2, res_ref = 0; + __mmask8 mask = MASK_VALUE; + + src.a[0] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = _mm_fpclass_sd_mask (src.x, 0xFF); + res2 = _mm_mask_fpclass_sd_mask (mask, src.x, 0xFF); + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((res_ref & mask) != res2) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c index 49050c95c26..4822441afa4 100644 --- a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-1.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-mavx512dq -O2" } */ /* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\](?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vfpclassss\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n^k\]*%k\[0-7\]\{%k\[0-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ #include @@ -11,4 +12,5 @@ void extern avx512dq_test (void) { m8 = _mm_fpclass_ss_mask (x128, 13); + m8 = _mm_mask_fpclass_ss_mask (m8, x128, 13); } diff --git a/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c new file mode 100644 index 00000000000..38fd6575adc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512dq-vfpclassss-2.c @@ -0,0 +1,76 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512dq" } */ +/* { dg-require-effective-target avx512dq } */ + +#define AVX512DQ +#include "avx512f-helper.h" + +#include +#include +#include +#include "avx512f-mask-type.h" +#define SIZE (128 / 32) + +#ifndef __FPCLASSSS__ +#define __FPCLASSSS__ +int check_fp_class_sp (float src, int imm) +{ + int qNaN_res = isnan (src); + int sNaN_res = isnan (src); + int Pzero_res = (src == 0.0); + int Nzero_res = (src == -0.0); + int PInf_res = (isinf (src) == 1); + int NInf_res = (isinf (src) == -1); + int Denorm_res = (fpclassify (src) == FP_SUBNORMAL); + int FinNeg_res = __builtin_finite (src) && (src < 0); + + int result = (((imm & 1) && qNaN_res) + || (((imm >> 1) & 1) && Pzero_res) + || (((imm >> 2) & 1) && Nzero_res) + || (((imm >> 3) & 1) && PInf_res) + || (((imm >> 4) & 1) && NInf_res) + || (((imm >> 5) & 1) && Denorm_res) + || (((imm >> 6) & 1) && FinNeg_res) + || (((imm >> 7) & 1) && sNaN_res)); + return result; +} +#endif + +__mmask8 +CALC (float *s1, int imm) +{ + int i; + __mmask8 res = 0; + + if (check_fp_class_sp(s1[0], imm)) + res = res | 1; + + return res; +} + +void +TEST (void) +{ + int i; + union128 src; + __mmask8 res1, res2, res_ref = 0; + __mmask8 mask = MASK_VALUE; + + src.a[0] = 1.0 / 0.0; + for (i = 1; i < SIZE; i++) + { + src.a[i] = -24.43 + 0.6 * i; + } + + res1 = _mm_fpclass_ss_mask (src.x, 0xFF); + res2 = _mm_mask_fpclass_ss_mask (mask, src.x, 0xFF); + + + res_ref = CALC (src.a, 0xFF); + + if (res_ref != res1) + abort (); + + if ((mask & res_ref) != res2) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index a16f9202ae3..91da5da0b96 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -461,8 +461,8 @@ #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E) #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) -#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) -#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U) #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D) diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index 7ac331ea84d..8b809acd71f 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -460,8 +460,8 @@ #define __builtin_ia32_inserti32x8_mask(A, B, F, D, E) __builtin_ia32_inserti32x8_mask(A, B, 1, D, E) #define __builtin_ia32_insertf64x2_512_mask(A, B, F, D, E) __builtin_ia32_insertf64x2_512_mask(A, B, 1, D, E) #define __builtin_ia32_insertf32x8_mask(A, B, F, D, E) __builtin_ia32_insertf32x8_mask(A, B, 1, D, E) -#define __builtin_ia32_fpclassss(A, D) __builtin_ia32_fpclassss(A, 1) -#define __builtin_ia32_fpclasssd(A, D) __builtin_ia32_fpclasssd(A, 1) +#define __builtin_ia32_fpclassss_mask(A, D, U) __builtin_ia32_fpclassss_mask(A, 1, U) +#define __builtin_ia32_fpclasssd_mask(A, D, U) __builtin_ia32_fpclasssd_mask(A, 1, U) #define __builtin_ia32_fpclassps512_mask(A, D, C) __builtin_ia32_fpclassps512_mask(A, 1, C) #define __builtin_ia32_fpclasspd512_mask(A, D, C) __builtin_ia32_fpclasspd512_mask(A, 1, C) #define __builtin_ia32_extracti64x2_512_mask(A, E, C, D) __builtin_ia32_extracti64x2_512_mask(A, 1, C, D)