From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 25 Sep 2023 17:40:51 +0000 (+0100)
Subject: add lbzup english description based on lbzu
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=526546593ade4d03be284c87a068d6cac8048c06;p=openpower-isa.git

add lbzup english description based on lbzu
---

diff --git a/openpower/isa/pifixedload.mdwn b/openpower/isa/pifixedload.mdwn
index b5671cbc..045d3262 100644
--- a/openpower/isa/pifixedload.mdwn
+++ b/openpower/isa/pifixedload.mdwn
@@ -20,6 +20,16 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- (RA) + EXTS(D)
 
+Description:
+
+    Let the effective address (EA) be register RA. The
+    byte in storage addressed by EA is loaded into RT[56:63].
+    RT[0:55] are set to 0.
+
+    The sum (RA) + D is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None