From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 1 Mar 2019 12:01:26 +0000 (+0000)
Subject: commennt use of intermediates
X-Git-Tag: ls180-24jan2020~1787
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5266edd6310043d3b99f8584a0d65742bd3670d9;p=ieee754fpu.git

commennt use of intermediates
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 704bdbd2..3a773260 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -415,7 +415,8 @@ class FPAddStage0Mod:
         #m.submodules.add0_out_z = self.out_z
 
         m.d.comb += self.out_z.e.eq(self.in_a.e)
-        # same-sign (both negative or both positive) add mantissas
+
+        # store intermediate tests (and zero-extended mantissas)
         seq = Signal(reset_less=True)
         mge = Signal(reset_less=True)
         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
@@ -425,6 +426,7 @@ class FPAddStage0Mod:
                      am0.eq(Cat(self.in_a.m, 0)),
                      bm0.eq(Cat(self.in_b.m, 0))
                     ]
+        # same-sign (both negative or both positive) add mantissas
         with m.If(seq):
             m.d.comb += [
                 self.out_tot.eq(am0 + bm0),