From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 27 Jul 2022 01:27:00 +0000 (+0100)
Subject: ARM NEON is PackedSIMD
X-Git-Tag: opf_rfc_ls005_v1~1020
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5268a5c602d288d3dc2d819ee1faad365a221093;p=libreriscv.git

ARM NEON is PackedSIMD
---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 48fabfc5c..aa9039a51 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -50,10 +50,11 @@ the provision of a `setvl` instruction, and why they are each called
 "Scalable" Vectors, because it is the `setvl` instruction that
 presents the **programmer** with explicit control over Vector length.
 
-ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
-**do not provide Scalability to the Programmer**.  SVE2 is **Silicon**
+VSX and NEON are PackedSIMD, and
+AVX-512 and ARM SVE2 are Predicated SIMD ISAs.
+**None of them provide Scalability to the Programmer**.  SVE2 is **Silicon**
 Scalable, not **Programmer** Scalable: the distinction is profoundly
-important.
+important (already causing problems).
 For Predicated SIMD, Programmers must emulate Cray-style scaling
 through explicit predicate masking, which increases instruction count in
 hot-loops.