From: Tim Newsome <tim@sifive.com>
Date: Thu, 21 Sep 2017 19:34:42 +0000 (-0700)
Subject: Fix debug reset.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=526d3997e68200ef3f372384acdc13e8e8b92e31;p=riscv-isa-sim.git

Fix debug reset.

ndmreset now resets all harts (instead of just the current hart), and
hartreset resets the selected hart (instead of being ignored).
---

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 53df8a4..8d73f07 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -459,10 +459,16 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value)
               debug_rom_flags[dmcontrol.hartsel] |= (1 << DEBUG_ROM_FLAG_RESUME);
               resumeack[dmcontrol.hartsel] = false;
             }
-	    if (dmcontrol.ndmreset) {
+	    if (dmcontrol.hartreset) {
 	      proc->reset();
 	    }
           }
+          if (dmcontrol.ndmreset) {
+            for (size_t i = 0; i < sim->nprocs(); i++) {
+              proc = sim->get_core(i);
+              proc->reset();
+            }
+          }
         }
         return true;