From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 22:15:43 +0000 (-0700)
Subject: Add arrival times for SRL outputs
X-Git-Tag: working-ls180~881^2^2~235
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=526e0813427aae24b9df2eacbbb8c067bdfd5eec;p=yosys.git

Add arrival times for SRL outputs
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 910d0e246..e5d9f480b 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -353,7 +353,8 @@ module RAM128X1D (
 endmodule
 
 module SRL16E (
-  output Q,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
   input A0, A1, A2, A3, CE, CLK, D
 );
   parameter [15:0] INIT = 16'h0000;
@@ -371,8 +372,9 @@ module SRL16E (
 endmodule
 
 module SRLC32E (
-  output Q,
-  output Q31,
+  // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+  (* abc_arrival=1472 *) output Q,
+  (* abc_arrival=1114 *) output Q31,
   input [4:0] A,
   input CE, CLK, D
 );