From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 30 Oct 2021 09:15:17 +0000 (+0200)
Subject: loadstore.py: add debug output for dcbz
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=528e55c1c721c98d3c0e7e41405e0790f7c106f8;p=soc.git

loadstore.py: add debug output for dcbz
---

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 7400c0ae..22acd797 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -128,6 +128,8 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.req.align_intr.eq(misalign)
         m.d.comb += self.req.dcbz.eq(is_dcbz)
 
+        m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz)
+
         # option to disable the cache entirely for write
         if self.disable_cache:
             m.d.comb += self.req.nc.eq(1)