From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 12 Jul 2016 05:45:55 +0000 (-0700)
Subject: Added GP_DAC cell
X-Git-Tag: yosys-0.7~174^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52a738a54435d9e54ac7cb523551ae866cc76770;p=yosys.git

Added GP_DAC cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index bf178a08a..ca8556a85 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 endmodule
 
+module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
+
+	initial VOUT = 0;
+
+	//analog hard IP is not supported for simulation
+
+endmodule
+
 module GP_DELAY(input IN, output reg OUT);
 	
 	parameter DELAY_STEPS = 1;