From: Tom Stellard Date: Mon, 7 May 2012 19:20:26 +0000 (-0400) Subject: radeon/llvm: Remove the ReorderPreloadInstructions pass X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52a7f212d36bd9829494bd588ecb9a3ebe9fc28a;p=mesa.git radeon/llvm: Remove the ReorderPreloadInstructions pass --- diff --git a/src/gallium/drivers/radeon/AMDGPU.h b/src/gallium/drivers/radeon/AMDGPU.h index eff002a5eae..aa590350dea 100644 --- a/src/gallium/drivers/radeon/AMDGPU.h +++ b/src/gallium/drivers/radeon/AMDGPU.h @@ -32,8 +32,6 @@ namespace llvm { FunctionPass *createSIPropagateImmReadsPass(TargetMachine &tm); FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); - FunctionPass *createAMDGPUReorderPreloadInstructionsPass(TargetMachine &tm); - FunctionPass *createAMDGPULowerInstructionsPass(TargetMachine &tm); FunctionPass *createAMDGPULowerShaderInstructionsPass(TargetMachine &tm); diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp index 4742283f688..ecd8ac90526 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp @@ -108,9 +108,4 @@ unsigned AMDGPUInstrInfo::getISAOpcode(unsigned opcode) const } } -bool AMDGPUInstrInfo::isRegPreload(const MachineInstr &MI) const -{ - return (get(MI.getOpcode()).TSFlags >> AMDGPU_TFLAG_SHIFTS::PRELOAD_REG) & 0x1; -} - #include "AMDGPUInstrEnums.include" diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h index fa009bc6302..ad135d46cb3 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h @@ -41,19 +41,9 @@ namespace llvm { virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const; - bool isRegPreload(const MachineInstr &MI) const; - #include "AMDGPUInstrEnums.h.include" }; } // End llvm namespace -/* AMDGPU target flags are stored in bits 32-39 */ -namespace AMDGPU_TFLAG_SHIFTS { - enum TFLAGS { - PRELOAD_REG = 32 - }; -} - - #endif // AMDGPUINSTRINFO_H_ diff --git a/src/gallium/drivers/radeon/AMDGPUInstructions.td b/src/gallium/drivers/radeon/AMDGPUInstructions.td index 0433c8dcd95..f5b87f3333a 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstructions.td +++ b/src/gallium/drivers/radeon/AMDGPUInstructions.td @@ -16,14 +16,12 @@ include "AMDGPUInstrEnums.td" class AMDGPUInst pattern> : Instruction { field bits<16> AMDILOp = 0; field bits<3> Gen = 0; - field bit PreloadReg = 0; let Namespace = "AMDIL"; let OutOperandList = outs; let InOperandList = ins; let AsmString = asm; let Pattern = pattern; - let TSFlags{32} = PreloadReg; let TSFlags{42-40} = Gen; let TSFlags{63-48} = AMDILOp; } @@ -48,9 +46,7 @@ let isCodeGenOnly = 1 in { (outs GPRF32:$dst), (ins i32imm:$src), "LOAD_INPUT $dst, $src", - [] >{ - let PreloadReg = 1; - } + [] >; def MASK_WRITE : AMDGPUShaderInst < (outs), @@ -63,9 +59,8 @@ let isCodeGenOnly = 1 in { (outs GPRF32:$dst), (ins i32imm:$src), "RESERVE_REG $dst, $src", - [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))]> { - let PreloadReg = 1; - } + [(set GPRF32:$dst, (int_AMDGPU_reserve_reg imm:$src))] + >; def STORE_OUTPUT: AMDGPUShaderInst < (outs GPRF32:$dst), diff --git a/src/gallium/drivers/radeon/AMDGPUReorderPreloadInstructions.cpp b/src/gallium/drivers/radeon/AMDGPUReorderPreloadInstructions.cpp deleted file mode 100644 index c923f19c39f..00000000000 --- a/src/gallium/drivers/radeon/AMDGPUReorderPreloadInstructions.cpp +++ /dev/null @@ -1,66 +0,0 @@ -//===-- AMDGPUReorderPreloadInstructions.cpp - TODO: Add brief description -------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// TODO: Add full description -// -//===----------------------------------------------------------------------===// - -#include "AMDGPU.h" -#include "AMDIL.h" -#include "AMDILInstrInfo.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Function.h" - -using namespace llvm; - -namespace { - class AMDGPUReorderPreloadInstructionsPass : public MachineFunctionPass { - - private: - static char ID; - TargetMachine &TM; - - public: - AMDGPUReorderPreloadInstructionsPass(TargetMachine &tm) : - MachineFunctionPass(ID), TM(tm) { } - - bool runOnMachineFunction(MachineFunction &MF); - - const char *getPassName() const { return "AMDGPU Reorder Preload Instructions"; } - }; -} /* End anonymous namespace */ - -char AMDGPUReorderPreloadInstructionsPass::ID = 0; - -FunctionPass *llvm::createAMDGPUReorderPreloadInstructionsPass(TargetMachine &tm) { - return new AMDGPUReorderPreloadInstructionsPass(tm); -} - -/* This pass moves instructions that represent preloaded registers to the - * start of the program. */ -bool AMDGPUReorderPreloadInstructionsPass::runOnMachineFunction(MachineFunction &MF) -{ - const AMDGPUInstrInfo * TII = - static_cast(TM.getInstrInfo()); - - for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); - BB != BB_E; ++BB) { - MachineBasicBlock &MBB = *BB; - for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I); - I != MBB.end(); I = Next, Next = llvm::next(I) ) { - MachineInstr &MI = *I; - if (TII->isRegPreload(MI)) { - MF.front().insert(MF.front().begin(), MI.removeFromParent()); - } - } - } - return false; -} diff --git a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp index 4357d198bbe..4f650dbaa46 100644 --- a/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp +++ b/src/gallium/drivers/radeon/AMDGPUTargetMachine.cpp @@ -127,7 +127,6 @@ bool AMDGPUPassConfig::addInstSelector() { bool AMDGPUPassConfig::addPreRegAlloc() { const AMDILSubtarget &ST = TM->getSubtarget(); - PM->add(createAMDGPUReorderPreloadInstructionsPass(*TM)); if (ST.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX) { PM->add(createR600LowerShaderInstructionsPass(*TM)); PM->add(createR600LowerInstructionsPass(*TM)); diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 6e649152120..9149cf3caf5 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -43,7 +43,6 @@ CPP_SOURCES := \ AMDGPUConvertToISA.cpp \ AMDGPULowerInstructions.cpp \ AMDGPULowerShaderInstructions.cpp \ - AMDGPUReorderPreloadInstructions.cpp \ AMDGPUInstrInfo.cpp \ AMDGPURegisterInfo.cpp \ AMDGPUUtil.cpp \ diff --git a/src/gallium/drivers/radeon/SICodeEmitter.cpp b/src/gallium/drivers/radeon/SICodeEmitter.cpp index ad494fae7c6..9ef6bcb4d8a 100644 --- a/src/gallium/drivers/radeon/SICodeEmitter.cpp +++ b/src/gallium/drivers/radeon/SICodeEmitter.cpp @@ -144,8 +144,6 @@ bool SICodeEmitter::runOnMachineFunction(MachineFunction &MF) { MF.dump(); TM = &MF.getTarget(); - const AMDGPUInstrInfo * TII = - static_cast(TM->getInstrInfo()); emitState(MF); @@ -155,8 +153,7 @@ bool SICodeEmitter::runOnMachineFunction(MachineFunction &MF) for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I) { MachineInstr &MI = *I; - if (!TII->isRegPreload(MI) && MI.getOpcode() != AMDIL::KILL - && MI.getOpcode() != AMDIL::RETURN) { + if (MI.getOpcode() != AMDIL::KILL && MI.getOpcode() != AMDIL::RETURN) { emitInstr(MI); } } diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 27a8b31757a..7fa397a31a3 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -833,7 +833,6 @@ def USE_SGPR_32 : InstSI < > { field bits<32> Inst = 0; - let PreloadReg = 1; } def USE_SGPR_64 : InstSI < @@ -844,7 +843,6 @@ def USE_SGPR_64 : InstSI < > { field bits<32> Inst = 0; - let PreloadReg = 1; } def VS_LOAD_BUFFER_INDEX : InstSI < @@ -854,7 +852,6 @@ def VS_LOAD_BUFFER_INDEX : InstSI < [(set VReg_32:$dst, (int_SI_vs_load_buffer_index))]> { field bits<32> Inst = 0; - let PreloadReg = 1; } } // end usesCustomInserter