From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 29 Jul 2020 14:16:30 +0000 (+0200)
Subject: Add more checks in delayed_enter
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52b783a65cc5c769fa47945a14308bc2415532dc;p=gram.git

Add more checks in delayed_enter
---

diff --git a/gram/compat.py b/gram/compat.py
index 6f72d5e..c053006 100644
--- a/gram/compat.py
+++ b/gram/compat.py
@@ -11,7 +11,12 @@ __ALL__ = ["delayed_enter", "Timeline", "CSRPrefixProxy"]
 
 
 def delayed_enter(m, src, dst, delay):
-    assert delay > 0
+    if not isinstance(m, Module):
+        raise ValueError("m must be a module object, not {!r}".format(m))
+    if not isinstance(delay, int):
+        raise ValueError("Delay must be an integer, not {!r}".format(delay))
+    if delay < 1:
+        raise ValueError("Delay must be at least one cycle, not {!r}".format(delay))
 
     for i in range(delay):
         if i == 0:
diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
index 4793472..4835bd5 100644
--- a/gram/test/test_compat.py
+++ b/gram/test/test_compat.py
@@ -37,7 +37,7 @@ class DelayedEnterTestCase(FHDLTestCase):
 
             runSimulation(m, process, "test_delayedenter.vcd")
 
-        with self.assertRaises(AssertionError):
+        with self.assertRaises(ValueError):
             sequence(0)
         sequence(1)
         sequence(2)