From: Gabe Black Date: Wed, 16 Oct 2019 04:20:39 +0000 (-0700) Subject: cpu: Turn the stage 2 ARM MMUs from params to children. X-Git-Tag: v19.0.0.0~429 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52d06fd655d36ac4a8ae09934e091cf2bacf578f;p=gem5.git cpu: Turn the stage 2 ARM MMUs from params to children. These aren't referred to in the C++, so there's no reason for them to be parameters. By making them children, they can still be modified, replaced wholesale, or even replaced by an entirely different object to, for instance, mask them when they're not needed. Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839 Reviewed-by: Jason Lowe-Power Reviewed-by: Andreas Sandberg Maintainer: Andreas Sandberg Tested-by: kokoro --- diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 85e37776e..143ee9224 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -182,8 +182,8 @@ class BaseCPU(ClockedObject): dtb = Param.BaseTLB(ArchDTB(), "Data TLB") itb = Param.BaseTLB(ArchITB(), "Instruction TLB") if buildEnv['TARGET_ISA'] == 'arm': - istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans") - dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans") + istage2_mmu = ArmStage2IMMU() + dstage2_mmu = ArmStage2DMMU() elif buildEnv['TARGET_ISA'] == 'power': UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") interrupts = ArchInterruptsParam([], "Interrupt Controller")