From: David Edelsohn Date: Sun, 28 Feb 1999 12:27:05 +0000 (-0500) Subject: [multiple changes] X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52d3af72b2dcb68e594e384ae2befb10b3dc6700;p=gcc.git [multiple changes] Sun Feb 28 15:10:17 1999 David Edelsohn * rs6000.md (elf_high, movsi_got, *movsi_got_internal, *movsi_got_internal_mem, GOT splitter, movdf_hardfloat32, movdf_softfloat32, movdf_hardfloat64, movdf_softfloat64, load_multiple, allocate_stack, call_indirect_aix32, call_indirect_aix64, call_value_indirect_aix32, call_value_indirect_aix64, call_indirect_nt, call_value_indirect_nt): Use gpc_reg_operand instead of register_operand. Sun Feb 28 15:10:17 1999 Michael Meissner * rs6000.md (one_cmplsi2, andsi3, iorsi3, xorsi3, *eqvsi3, *andcsi3, *iorcsi3, *nandsi3, *norsi3): Add alternatives to use CR other than cr0. * rs6000.c (and{,64}_operand): If the user did -ffixed-cr0, don't allow andi. or andis. which always set cr0. From-SVN: r25501 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e38218b0345..a8367db938a 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,22 @@ +Sun Feb 28 15:10:17 1999 David Edelsohn + + * rs6000.md (elf_high, movsi_got, *movsi_got_internal, + *movsi_got_internal_mem, GOT splitter, movdf_hardfloat32, + movdf_softfloat32, movdf_hardfloat64, movdf_softfloat64, + load_multiple, allocate_stack, call_indirect_aix32, + call_indirect_aix64, call_value_indirect_aix32, + call_value_indirect_aix64, call_indirect_nt, + call_value_indirect_nt): Use gpc_reg_operand instead of + register_operand. + +Sun Feb 28 15:10:17 1999 Michael Meissner + + * rs6000.md (one_cmplsi2, andsi3, iorsi3, xorsi3, *eqvsi3, + *andcsi3, *iorcsi3, *nandsi3, *norsi3): Add alternatives to use CR + other than cr0. + * rs6000.c (and{,64}_operand): If the user did -ffixed-cr0, don't + allow andi. or andis. which always set cr0. + Sun Feb 28 01:15:04 PST 1999 Jeff Law (law@cygnus.com) * version.c: Bump for snapshot. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a2bfcca9f27..c158fc3a3b5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -1041,8 +1041,10 @@ and64_operand (op, mode) register rtx op; enum machine_mode mode; { - return (logical_operand (op, mode) - || mask64_operand (op, mode)); + if (fixed_regs[68]) /* CR0 not available, don't do andi./andis. */ + return (gpc_reg_operand (op, mode) || mask64_operand (op, mode)); + + return (logical_operand (op, mode) || mask64_operand (op, mode)); } /* Return 1 if the operand is either a non-special register or a @@ -1053,8 +1055,10 @@ and_operand (op, mode) register rtx op; enum machine_mode mode; { - return (logical_operand (op, mode) - || mask_operand (op, mode)); + if (fixed_regs[68]) /* CR0 not available, don't do andi./andis. */ + return (gpc_reg_operand (op, mode) || mask_operand (op, mode)); + + return (logical_operand (op, mode) || mask_operand (op, mode)); } /* Return 1 if the operand is a general register or memory operand. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 67bfe8d94f8..cbfafd9606c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -1018,23 +1018,56 @@ "nor %0,%1,%1") (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 2 "=r"))] + (clobber (match_scratch:SI 2 "=r,r"))] "" - "nor. %2,%1,%1" - [(set_attr "type" "compare")]) + "@ + nor. %2,%1,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 2 ""))] + "reload_completed" + [(set (match_dup 2) + (not:SI (match_dup 1))) + (set (match_dup 0) + (compare:CC (match_dup 2) + (const_int 0)))] + "") (define_insn "" - [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (not:SI (match_dup 1)))] "" - "nor. %0,%1,%1" - [(set_attr "type" "compare")]) + "@ + nor. %0,%1,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (match_dup 1)))] + "reload_completed" + [(set (match_dup 0) + (not:SI (match_dup 1))) + (set (match_dup 2) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1828,36 +1861,89 @@ {rlinm|rlwinm} %0,%1,0,%m2,%M2 {andil.|andi.} %0,%1,%b2 {andiu.|andis.} %0,%1,%u2" - [(set_attr "length" "4,4,4,4")]) + [(set_attr "length" "4")]) + +;; Note to set cr's other than cr0 we do the and immediate and then +;; the test again -- this avoids a mcrf which on the higher end +;; machines causes an execution serialization (define_insn "*andsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] + (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] "" "@ and. %3,%1,%2 {andil.|andi.} %3,%1,%b2 {andiu.|andis.} %3,%1,%u2 - {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" - [(set_attr "type" "compare,compare,compare,delayed_compare")]) + {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "and_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 "")) + (clobber (match_scratch:CC 4 ""))] + "reload_completed" + [(parallel [(set (match_dup 3) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*andsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:SI 2 "and_operand" "r,K,J,L")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (and:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] "" "@ and. %0,%1,%2 {andil.|andi.} %0,%1,%b2 {andiu.|andis.} %0,%1,%u2 - {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" - [(set_attr "type" "compare,compare,compare,delayed_compare")]) + {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "and_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 ""))] + "reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1893,25 +1979,63 @@ [(set_attr "length" "4,4,4")]) (define_insn "*iorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "or. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + or. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*iorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ior:SI (match_dup 1) + (match_dup 2)))] "" - "or. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + or. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; Split an IOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -1963,25 +2087,63 @@ [(set_attr "length" "4,4,4")]) (define_insn "*xorsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "xor. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + xor. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*xorsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (xor:SI (match_dup 1) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (xor:SI (match_dup 1) + (match_dup 2)))] "" - "xor. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + xor. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (xor:SI (match_dup 1) (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (xor:SI (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; Split an XOR that we can't do in one insn into two insns, each of which ;; does one 16-bit part. This is used by combine. @@ -2007,25 +2169,63 @@ "eqv %0,%1,%2") (define_insn "*eqvsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "eqv. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + eqv. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (not:SI (xor:SI (match_dup 1) + (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*eqvsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") - (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") + (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" - "eqv. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + eqv. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_short_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (not:SI (xor:SI (match_dup 1) + (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (not:SI (xor:SI (match_dup 1) + (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*andcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2035,25 +2235,64 @@ "andc %0,%2,%1") (define_insn "*andcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "andc. %3,%2,%1" - [(set_attr "type" "compare")]) + "@ + andc. %3,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (and:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*andcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_dup 1)) (match_dup 2)))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (not:SI (match_dup 1)) + (match_dup 2)))] "" - "andc. %0,%2,%1" - [(set_attr "type" "compare")]) + "@ + andc. %0,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (not:SI (match_dup 1)) + (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*iorcsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2063,26 +2302,63 @@ "orc %0,%2,%1") (define_insn "*iorcsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "orc. %3,%2,%1" - [(set_attr "type" "compare")]) + "@ + orc. %3,%2,%1 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*iorcsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) - (match_operand:SI 2 "gpc_reg_operand" "r")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) + (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] "" - "orc. %0,%2,%1" + "@ + orc. %0,%2,%1 + #" [(set_attr "type" "compare")]) +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (not:SI (match_dup 1)) + (match_dup 2)))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (not:SI (match_dup 1)) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + (define_insn "*nandsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) @@ -2091,25 +2367,64 @@ "nand %0,%1,%2") (define_insn "*nandsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "nand. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + nand. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*nandsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] "" - "nand. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + nand. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (ior:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") (define_insn "*norsi3_internal1" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -2119,25 +2434,64 @@ "nor %0,%1,%2") (define_insn "*norsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (clobber (match_scratch:SI 3 "=r"))] + (clobber (match_scratch:SI 3 "=r,r"))] "" - "nor. %3,%1,%2" - [(set_attr "type" "compare")]) + "@ + nor. %3,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "reload_completed" + [(set (match_dup 3) + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") (define_insn "*norsi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) - (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r") - (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] "" - "nor. %0,%1,%2" - [(set_attr "type" "compare")]) + "@ + nor. %0,%1,%2 + #" + [(set_attr "type" "compare") + (set_attr "length" "4,8")]) + +(define_split + [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2))))] + "reload_completed" + [(set (match_dup 0) + (and:SI (not:SI (match_dup 1)) + (not:SI (match_dup 2)))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") ;; maskir insn. We need four forms because things might be in arbitrary ;; orders. Don't define forms that only set CR fields because these @@ -5412,14 +5766,14 @@ ;; registers, since almost all uses of this will need it ;; in a base register shortly. (define_insn "elf_high" - [(set (match_operand:SI 0 "register_operand" "=b") + [(set (match_operand:SI 0 "gpc_reg_operand" "=b") (high:SI (match_operand 1 "" "")))] "TARGET_ELF && !TARGET_64BIT" "{liu|lis} %0,%1@ha") (define_insn "elf_low" - [(set (match_operand:SI 0 "register_operand" "=r") - (lo_sum:SI (match_operand:SI 1 "register_operand" "b") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" "")))] "TARGET_ELF && !TARGET_64BIT" "{cal|la} %0,%2@l(%1)") @@ -5427,7 +5781,7 @@ ;; Set up a register with a value from the GOT table (define_expand "movsi_got" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") (unspec [(match_operand:SI 1 "got_operand" "") (match_dup 2)] 8))] "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" @@ -5455,9 +5809,9 @@ }") (define_insn "*movsi_got_internal" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec [(match_operand:SI 1 "got_no_const_operand" "") - (match_operand:SI 2 "register_operand" "b")] 8))] + (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" "{l|lwz} %0,%a1@got(%2)" [(set_attr "type" "load")]) @@ -5467,7 +5821,7 @@ ;; Force final to split this insn (if it hasn't been split already) to ;; avoid having to create a suitable output template. (define_insn "*movsi_got_internal_mem" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec [(match_operand:SI 1 "got_no_const_operand" "") (match_operand:SI 2 "memory_operand" "m")] 8))] "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) @@ -5480,7 +5834,7 @@ ;; Used by sched, shorten_branches and final when the GOT pseudo reg ;; didn't get allocated to a hard register. (define_split - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec [(match_operand:SI 1 "got_no_const_operand" "") (match_operand:SI 2 "memory_operand" "m")] 8))] "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) @@ -5981,8 +6335,8 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m") (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT - && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode))" "* { switch (which_alternative) @@ -6028,8 +6382,8 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT - && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode))" "* { switch (which_alternative) @@ -6069,8 +6423,8 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT - && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode))" "@ mr %0,%1 ld%U1%X1 %0,%1 @@ -6088,8 +6442,8 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] "TARGET_POWERPC64 && TARGET_SOFT_FLOAT - && (register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode))" "@ mr %0,%1 ld%U1%X1 %0,%1 @@ -6624,7 +6978,7 @@ (define_insn "" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:SI 1 "gpc_reg_operand" "=r") - (mem:SI (match_operand:SI 2 "register_operand" "b")))])] + (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] "TARGET_STRING" "* { @@ -6735,7 +7089,7 @@ (define_insn "" [(match_parallel 0 "store_multiple_operation" - [(set (mem:SI (match_operand:SI 1 "register_operand" "b")) + [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) (match_operand:SI 2 "gpc_reg_operand" "r")) (clobber (match_scratch:SI 3 "X"))])] "TARGET_STRING && !TARGET_POWER" @@ -6783,11 +7137,11 @@ "") (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 6)) (clobber (reg:SI 7)) (clobber (reg:SI 8)) @@ -6806,11 +7160,11 @@ (set_attr "length" "8")]) (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 6)) (clobber (reg:SI 7)) (clobber (reg:SI 8)) @@ -6846,11 +7200,11 @@ "") (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 8)) (clobber (reg:SI 9)) (clobber (reg:SI 10)) @@ -6867,11 +7221,11 @@ (set_attr "length" "8")]) (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 8)) (clobber (reg:SI 9)) (clobber (reg:SI 10)) @@ -6903,11 +7257,11 @@ "") (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 10)) (clobber (reg:SI 11)) (clobber (reg:SI 12)) @@ -6922,11 +7276,11 @@ (set_attr "length" "8")]) (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) - (clobber (match_operand:SI 4 "register_operand" "=r")) + (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) (clobber (reg:SI 10)) (clobber (reg:SI 11)) (clobber (reg:SI 12)) @@ -6952,8 +7306,8 @@ "") (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_scratch:DI 4 "=&r")) @@ -6965,8 +7319,8 @@ (set_attr "length" "8")]) (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_scratch:DI 4 "=&r")) @@ -6989,8 +7343,8 @@ "") (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_scratch:SI 4 "=&r")) @@ -7002,8 +7356,8 @@ (set_attr "length" "8")]) (define_insn "" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) - (mem:BLK (match_operand:SI 1 "register_operand" "b"))) + [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) + (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) (use (match_operand:SI 2 "immediate_operand" "i")) (use (match_operand:SI 3 "immediate_operand" "i")) (clobber (match_scratch:SI 4 "=&r")) @@ -7274,7 +7628,7 @@ ;; We move the back-chain and decrement the stack pointer. (define_expand "allocate_stack" - [(set (match_operand 0 "register_operand" "=r") + [(set (match_operand 0 "gpc_reg_operand" "=r") (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) (set (reg 1) (minus (reg 1) (match_dup 1)))] @@ -7434,12 +7788,12 @@ ;; to move the load of the new TOC before any loads from the TOC. (define_insn "call_indirect_aix32" - [(call (mem:SI (match_operand:SI 0 "register_operand" "b")) + [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) (match_operand 1 "const_int_operand" "n")) (use (match_operand 2 "const_int_operand" "n")) (use (match_operand 3 "offsettable_mem_operand" "o")) - (use (match_operand 4 "register_operand" "r")) - (clobber (match_operand 5 "register_operand" "=r")) + (use (match_operand 4 "gpc_reg_operand" "r")) + (clobber (match_operand 5 "gpc_reg_operand" "=r")) (clobber (match_scratch:SI 6 "=&r")) (clobber (match_scratch:SI 7 "=l"))] "DEFAULT_ABI == ABI_AIX @@ -7449,12 +7803,12 @@ (set_attr "length" "28")]) (define_insn "call_indirect_aix64" - [(call (mem:SI (match_operand:DI 0 "register_operand" "b")) + [(call (mem:SI (match_operand:DI 0 "gpc_reg_operand" "b")) (match_operand 1 "const_int_operand" "n")) (use (match_operand 2 "const_int_operand" "n")) (use (match_operand 3 "offsettable_mem_operand" "o")) - (use (match_operand 4 "register_operand" "r")) - (clobber (match_operand 5 "register_operand" "=r")) + (use (match_operand 4 "gpc_reg_operand" "r")) + (clobber (match_operand 5 "gpc_reg_operand" "=r")) (clobber (match_scratch:SI 6 "=&r")) (clobber (match_scratch:SI 7 "=l"))] "TARGET_64BIT && DEFAULT_ABI == ABI_AIX @@ -7465,12 +7819,12 @@ (define_insn "call_value_indirect_aix32" [(set (match_operand 0 "register_operand" "fg") - (call (mem:SI (match_operand:SI 1 "register_operand" "b")) + (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) (match_operand 2 "const_int_operand" "n"))) (use (match_operand 3 "const_int_operand" "n")) (use (match_operand 4 "offsettable_mem_operand" "o")) - (use (match_operand 5 "register_operand" "r")) - (clobber (match_operand 6 "register_operand" "=r")) + (use (match_operand 5 "gpc_reg_operand" "r")) + (clobber (match_operand 6 "gpc_reg_operand" "=r")) (clobber (match_scratch:SI 7 "=&r")) (clobber (match_scratch:SI 8 "=l"))] "DEFAULT_ABI == ABI_AIX @@ -7481,12 +7835,12 @@ (define_insn "call_value_indirect_aix64" [(set (match_operand 0 "register_operand" "fg") - (call (mem:SI (match_operand:DI 1 "register_operand" "b")) + (call (mem:SI (match_operand:DI 1 "gpc_reg_operand" "b")) (match_operand 2 "const_int_operand" "n"))) (use (match_operand 3 "const_int_operand" "n")) (use (match_operand 4 "offsettable_mem_operand" "o")) - (use (match_operand 5 "register_operand" "r")) - (clobber (match_operand 6 "register_operand" "=r")) + (use (match_operand 5 "gpc_reg_operand" "r")) + (clobber (match_operand 6 "gpc_reg_operand" "=r")) (clobber (match_scratch:SI 7 "=&r")) (clobber (match_scratch:SI 8 "=l"))] "TARGET_64BIT && DEFAULT_ABI == ABI_AIX @@ -7510,11 +7864,11 @@ ;; to move the load of the new TOC before any loads from the TOC. (define_insn "call_indirect_nt" - [(call (mem:SI (match_operand:SI 0 "register_operand" "b")) + [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) (match_operand 1 "const_int_operand" "n")) (use (match_operand 2 "const_int_operand" "n")) (use (match_operand 3 "offsettable_mem_operand" "o")) - (use (match_operand 4 "register_operand" "r")) + (use (match_operand 4 "gpc_reg_operand" "r")) (clobber (match_scratch:SI 5 "=&r")) (clobber (match_scratch:SI 6 "=l"))] "DEFAULT_ABI == ABI_NT @@ -7525,11 +7879,11 @@ (define_insn "call_value_indirect_nt" [(set (match_operand 0 "register_operand" "fg") - (call (mem:SI (match_operand:SI 1 "register_operand" "b")) + (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) (match_operand 2 "const_int_operand" "n"))) (use (match_operand 3 "const_int_operand" "n")) (use (match_operand 4 "offsettable_mem_operand" "o")) - (use (match_operand 5 "register_operand" "r")) + (use (match_operand 5 "gpc_reg_operand" "r")) (clobber (match_scratch:SI 6 "=&r")) (clobber (match_scratch:SI 7 "=l"))] "DEFAULT_ABI == ABI_NT