From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 14:46:56 +0000 (+0100)
Subject: add sesvstate / mesvstate, set on entry to trap
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=52f7b4dd3800d1e70d4e8d8e26a757d81acbe66b;p=riscv-isa-sim.git

add sesvstate / mesvstate, set on entry to trap
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0a9d9f9..583e4c9 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -355,6 +355,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   // by default, trap to M-mode, unless delegated to S-mode
   reg_t bit = t.cause();
   reg_t deleg = state.medeleg;
+  reg_t svstate = get_csr(CSR_SV_STATE);
   bool interrupt = (bit & ((reg_t)1 << (max_xlen-1))) != 0;
   if (interrupt)
     deleg = state.mideleg, bit &= ~((reg_t)1 << (max_xlen-1));
@@ -363,6 +364,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     state.pc = state.stvec;
     state.scause = t.cause();
     state.sepc = epc;
+    state.sesvstate = svstate;
     state.stval = t.get_tval();
 
     reg_t s = state.mstatus;
@@ -375,6 +377,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     reg_t vector = (state.mtvec & 1) && interrupt ? 4*bit : 0;
     state.pc = (state.mtvec & ~(reg_t)1) + vector;
     state.mepc = epc;
+    state.mesvstate = svstate;
     state.mcause = t.cause();
     state.mtval = t.get_tval();
 
@@ -779,11 +782,13 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode)
       break;
     }
     case CSR_SEPC: state.sepc = val & ~(reg_t)1; break;
+    case CSR_SESVSTATE: state.sesvstate = val; break;
     case CSR_STVEC: state.stvec = val >> 2 << 2; break;
     case CSR_SSCRATCH: state.sscratch = val; break;
     case CSR_SCAUSE: state.scause = val; break;
     case CSR_STVAL: state.stval = val; break;
     case CSR_MEPC: state.mepc = val & ~(reg_t)1; break;
+    case CSR_MESVSTATE: state.mesvstate = val; break;
     case CSR_MTVEC: state.mtvec = val & ~(reg_t)2; break;
     case CSR_MSCRATCH: state.mscratch = val; break;
     case CSR_MCAUSE: state.mcause = val; break;
@@ -970,6 +975,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_SIP: return state.mip & state.mideleg;
     case CSR_SIE: return state.mie & state.mideleg;
     case CSR_SEPC: return state.sepc & pc_alignment_mask();
+    case CSR_SESVSTATE: return state.sesvstate;
     case CSR_STVAL: return state.stval;
     case CSR_STVEC: return state.stvec;
     case CSR_SCAUSE:
@@ -985,6 +991,7 @@ reg_t processor_t::get_csr(int which)
     case CSR_MIP: return state.mip;
     case CSR_MIE: return state.mie;
     case CSR_MEPC: return state.mepc & pc_alignment_mask();
+    case CSR_MESVSTATE: return state.mesvstate;
     case CSR_MSCRATCH: return state.mscratch;
     case CSR_MCAUSE: return state.mcause;
     case CSR_MTVAL: return state.mtval;
diff --git a/riscv/processor.h b/riscv/processor.h
index 8ebade9..4d4bf81 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -165,6 +165,8 @@ struct state_t
   sv_csr_t msv;
   sv_csr_t ssv;
   sv_csr_t usv;
+  reg_t sesvstate;
+  reg_t mesvstate;
 
   int sv_csr_sz();
   sv_csr_t &sv();