From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 15 Oct 2015 13:19:23 +0000 (+0200)
Subject: Fixed bug in verilog parser
X-Git-Tag: yosys-0.6~105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5308c1e02a4867b184efd8cbb419c058032d06b4;p=yosys.git

Fixed bug in verilog parser
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e0446e082..09748eba4 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -759,7 +759,7 @@ assign_expr_list:
 	assign_expr | assign_expr_list ',' assign_expr;
 
 assign_expr:
-	expr '=' expr {
+	lvalue '=' expr {
 		ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3));
 	};