From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 12:47:12 +0000 (+0100)
Subject: start using Data in pipelines
X-Git-Tag: div_pipeline~887
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53126de0ba6eb3c2b03a33248678358b90fc98f8;p=soc.git

start using Data in pipelines
---

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 3a9916a1..147c891e 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -18,9 +18,9 @@ class CommonOutputStage(PipeModBase):
         # op requests inversion of the output
         o = Signal.like(self.i.o)
         with m.If(op.invert_out):
-            comb += o.eq(~self.i.o)
+            comb += o.eq(~self.i.o.data)
         with m.Else():
-            comb += o.eq(self.i.o)
+            comb += o.eq(self.i.o.data)
 
         # target register if 32-bit is only the 32 LSBs
         target = Signal(64, reset_less=True)
@@ -58,7 +58,8 @@ class CommonOutputStage(PipeModBase):
             comb += cr0.eq(self.i.cr0)
 
         # copy out [inverted] cr0, output, and context out
-        comb += self.o.o.eq(o)
+        comb += self.o.o.data.eq(o)
+        comb += self.o.o.ok.eq(self.i.o.ok)
         comb += self.o.cr0.data.eq(cr0)
         comb += self.o.cr0.ok.eq(op.rc.rc & op.rc.rc_ok) # CR0 to be set
         comb += self.o.ctx.eq(self.i.ctx)
diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 16b45530..6b6f20a8 100644
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -30,6 +30,7 @@ class ShiftRotMainStage(PipeModBase):
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
+        o = self.o.o
 
         # obtain me and mb fields from instruction.
         m_fields = self.fields.instrs['M']
@@ -54,6 +55,8 @@ class ShiftRotMainStage(PipeModBase):
             rotator.arith.eq(op.is_signed),
         ]
 
+        comb += o.ok.eq(1) # defaults to enabled
+
         # instruction rotate type
         mode = Signal(3, reset_less=True)
         with m.Switch(op.insn_type):
@@ -62,6 +65,8 @@ class ShiftRotMainStage(PipeModBase):
             with m.Case(InternalOp.OP_RLC):  comb += mode.eq(0b110) # clear LR
             with m.Case(InternalOp.OP_RLCL): comb += mode.eq(0b010) # clear L
             with m.Case(InternalOp.OP_RLCR): comb += mode.eq(0b100) # clear R
+            with m.Default():
+                comb += o.ok.eq(0) # otherwise disable
 
         comb += Cat(rotator.right_shift,
                     rotator.clear_left,
@@ -69,7 +74,7 @@ class ShiftRotMainStage(PipeModBase):
                 
         # outputs from the microwatt rotator module
         # XXX TODO: carry32
-        comb += [self.o.o.eq(rotator.result_o),
+        comb += [o.data.eq(rotator.result_o),
                  self.o.xer_ca[0].eq(rotator.carry_out_o)]
 
         ###### sticky overflow and context, both pass-through #####
diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index 2d6fb8e1..8b942fcf 100644
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -237,7 +237,7 @@ class TestRunner(FHDLTestCase):
                         yield
                         vld = yield alu.n.valid_o
                     yield
-                    alu_out = yield alu.n.data_o.o
+                    alu_out = yield alu.n.data_o.o.data
                     out_reg_valid = yield pdecode2.e.write_reg.ok
                     if out_reg_valid:
                         write_reg_idx = yield pdecode2.e.write_reg.data
@@ -246,6 +246,7 @@ class TestRunner(FHDLTestCase):
                         self.assertEqual(expected, alu_out, msg)
                     yield from self.check_extra_alu_outputs(alu, pdecode2,
                                                             simulator)
+                    break
 
         sim.add_sync_process(process)
         with sim.write_vcd("simulator.vcd", "simulator.gtkw",