From: Xiaoyu Ma Date: Thu, 30 Nov 2017 15:48:52 +0000 (-0800) Subject: sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). X-Git-Tag: v19.0.0.0~2379 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5320a97ced43d4452014ff54c0ba45246db90a00;p=gem5.git sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy(). Before this CL, the addTwoLevelCacheHierarchy() function uses the default L2XBar class as the interconnect between CPU L1 caches and L2. This CL allows passing a user-defined bus to overwrite the default L2XBar by adding an optional argument to the function. Change-Id: I917657272fd4924ee0bed882a226851afba26847 Reviewed-on: https://gem5-review.googlesource.com/7364 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c100f0ed5..3e82daf29 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -299,9 +299,10 @@ class BaseCPU(MemObject): self._cached_ports += ["checker.itb.walker.port", \ "checker.dtb.walker.port"] - def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): + def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, + xbar=None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) - self.toL2Bus = L2XBar() + self.toL2Bus = xbar if xbar else L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side